Patents by Inventor Ming An

Ming An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES
    Publication number: 20230386914
    Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming a contact opening in an interlayer dielectric (ILD) layer disposed over an epitaxy source/drain region and forming a metal layer in the contact opening. The metal layer includes top portions, side portions, and a bottom portion, and a space is defined between the top portions of the metal layer. The method further includes performing a gradient metal removal process on the metal layer to enlarge the space, forming a sacrificial layer in the contact opening, recessing the sacrificial layer in the contact opening to expose a portion of the sidewall portions, removing the top portions and the exposed portion of the sidewall portions, removing the sacrificial layer, and forming a bulk metal layer on the bottom portion of the metal layer.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: Yu-Chen KO, Kai-Chieh YANG, Yu-Ting WEN, Ya-Yi CHENG, Min-Hsiu HUNG, Wei-Jung LIN, Chih-Wei CHANG, Ming-Hsing TSAI
  • MEMORY DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20230389300
    Abstract: Provided is a memory device and a method of forming the same. The method includes: providing a substrate having multiple active regions; forming a first layer stack on the substrate; patterning the first layer stack to form multiple recesses in the first layer stack; forming a liner layer on the first layer stack to cover the recesses; performing an etching process to remove a portion of the liner layer and the first layer stack below the recesses, so as to extend the recesses downward to form multiple openings, wherein the openings respectively expose the active regions; respectively forming multiple conductive structures in the openings; forming a second layer stack on the conductive structures; and patterning the second layer stack and the conductive structures to form multiple bit-line structures and bit-line contacts, respectively.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 30, 2023
    Applicant: Winbond Electronics Corp.
    Inventors: Yuan-Hao Su, Chun-Chieh Wang, Tzu-Ming Ou Yang
  • COSMETIC COMPACT WITH WIRELESS CHARGING
    Publication number: 20230387720
    Abstract: A compact includes a lower portion, an upper portion, a first mirror, a battery, a circuit, and a coil. The upper portion is movably coupled to the lower portion by a hinge such that the upper portion rotates about the hinge to transition from a closed state to an open state. The first mirror is disposed in the lower portion such that the first mirror is visible when the upper portion is in the open state. The battery is disposed within the lower portion. The circuit is electrically coupled to the battery. The coil is disposed within the upper portion and electrically coupled to the circuit such that the coil produces an oscillating magnetic field when electric power is provided to the coil by the battery and through the circuit.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventor: Lenny Kwok Ming LO
  • POLISHING METROLOGY
    Publication number: 20230381911
    Abstract: Methods and system for chemical mechanical polishing (CMP) are provided. A method may include performing a CMP process by contacting a polishing pad and a substrate at an interface. During the CMP process, the method includes measuring a force on the polishing pad at the interface to obtain force measurement values. Also, the method includes determining when the CMP process is complete based on the force measurement values.
    Type: Application
    Filed: August 29, 2022
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Hung CHEN, Kei-Wei CHEN, Syun-Ming Jang
  • DUAL-MODE WIRELESS CHARGING DEVICE
    Publication number: 20230387003
    Abstract: A method of making a semiconductor device, includes: forming a first molding layer on a substrate; forming a first plurality of vias in the first molding layer; forming a first conductive line over the first molding layer, wherein the first conductive line is laterally disposed over the first molding layer and a first end of the conductive line aligns with and is electrically coupled to a first via of the first plurality of vias; forming a second molding layer above the first molding layer; and forming a second plurality of vias in the second molding layer, wherein a second via of the second plurality of vias aligns with and is electrically coupled to a second end of the conductive line, and wherein the second plurality of vias, the conductive line, and the first plurality of vias are electrically coupled to one another.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Shih-Wei LIANG, Hung-Yi KUO, Hao-Yi TSAI, Ming-Hung TSENG, Hsien-Ming TU
  • Method and System for Repairing Device Tree, and Computer-Readable Storage Medium
    Publication number: 20230385046
    Abstract: A method for repairing a device tree includes: a development device performing differential processing on device tree source data and device tree target data to obtain patch data; the development device sending the patch data to user equipment; the user equipment patching an original device tree image file by using the patch data; and the user equipment repairing the original device tree image file to obtain an updated device tree image file.
    Type: Application
    Filed: August 13, 2021
    Publication date: November 30, 2023
    Inventor: Ming Gao
  • GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME
    Publication number: 20230387203
    Abstract: Depositing gallium nitride and carbon (GaN:C) (e.g., in the form of composite layers) when forming a gallium nitride drain of a transistor provides a buffer between the gallium nitride of the drain and silicon of a substrate in which the drain is formed. As a result, gaps and other defects caused by lattice mismatch are reduced, which improves electrical performance of the drain. Additionally, current leakage into the substrate is reduced, which further improves electrical performance of the drain. Additionally, or alternatively, implanting silicon in an aluminum nitride (AlN) liner for a gallium nitride drain reduces contact resistance at an interface between the gallium nitride and the silicon. As a result, electrical performance of the transistor is improved.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Chi-Ming CHEN, Kuei-Ming CHEN, Yung-Chang CHANG
  • MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20230389439
    Abstract: A memory device includes a substrate, a spin-orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) film stack, a connecting via and a shielding structure. The SOT layer is disposed on the substrate. The MTJ film stack is formed over SOT layer and on the substrate. The connecting via is disposed on and electrically connected to the MTJ film stack. The shielding structure is laterally surrounding the MTJ film stack and disposed on the SOT layer, wherein the shielding structure includes a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the SOT layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.
    Type: Application
    Filed: May 30, 2022
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Lin Huang, Ming-Yuan Song, Chien-Min Lee, Nuo Xu, Shy-Jay Lin
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230387125
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien HUANG, Che-Ming HSU, Ching-Feng FU, Huan-Just LIN
  • Controlling Fin-Thinning Through Feedback
    Publication number: 20230387263
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 30, 2023
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Communication Method, Communication Apparatus, and Communication Device
    Publication number: 20230388073
    Abstract: A communication method includes: generating an extremely high-throughput physical layer protocol data unit (EHT PPDU) that comprises a legacy physical layer preamble and a new physical layer preamble, wherein the legacy physical layer preamble comprises a legacy short training field (L-STF), a legacy long training field (L-LTF), and a legacy signal (L-SIG) field in turn, and wherein a first field of the new physical layer preamble is a repeat of a field in the legacy physical layer preamble and is modulated by binary phase shift keying, BPSK; and sending the PPDU.
    Type: Application
    Filed: May 24, 2023
    Publication date: November 30, 2023
    Inventors: Ming Gan, Wei Lin, Xun Yang
  • METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
    Publication number: 20230386940
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming an interconnect structure, and forming a conductive feature electrically connected to the interconnect structure. The method also includes forming a first passivation layer over the interconnect structure and the conductive feature, and etching the first passivation layer to form an opening that exposes the conductive feature. The method further includes performing an electrical test on the conductive feature, filling the opening with an oxide material, and attaching a carrier substrate over the oxide material using a bonding layer.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Yang, Dian-Hau Chen, Yen-Ming Chen
  • SYNTHESIS AND USES OF GINSENOSIDE COMPOUND K DERIVATIVES
    Publication number: 20230381213
    Abstract: A nontoxic anticancer compound is a derivative of 20-O-?-(D-glucopyranosyl)-20(S)-protopanaxadiol (CK) having at least one of the glucose hydroxyl groups replaced with at least one acetal group. The derivative enhances binding to a mitochondrial membrane protein and is more cytotoxic to cancerous cells than CK. The derivative can be an acetal of an unsubstituted or substituted aromatic group, such as an acetal formed from a substituted 1-(dimethoxymethyl)-benzene. One or more of the CK derivative (CKD) anticancer compounds can be used as an active portion of an anticancer medicament.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 30, 2023
    Inventors: Chi-Ming CHE, Yungen LIU, Jilin HE, Chun-Nam LOK
  • ELECTRONIC DEVICE
    Publication number: 20230384642
    Abstract: The disclosure provides an electronic device including a substrate, two adjacent first lines, two adjacent second lines and an opening. Two adjacent first lines extending along a first direction, two adjacent first lines and two disposed adjacent second lines are disposed on the substrate. The pixel is defined by the two adjacent first lines and the two adjacent second lines. The opening is corresponding to the pixel, and an edge of the opening is adjacent to an edge of one of the two adjacent first lines. A distance between the edge of the opening and the edge of the one of the two adjacent first lines is from 1 micrometer to 2 micrometers. The opening comprises a first arc portion and a second arc portion, and the first arc portion and the second arc portion are disposed at diagonal corners of the opening.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 30, 2023
    Applicant: Innolux Corporation
    Inventors: Ming-Jou Tai, Chia-Hao Tsai, Yu-Shih Tsou
  • HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER
    Publication number: 20230386938
    Abstract: A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Huiching Chang, I-Ming Chang, Huang-Lin Chao
  • SEMICONDUCTOR ARRANGEMENT WITH ISOLATION STRUCTURE
    Publication number: 20230387168
    Abstract: A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Feng-Chien HSIEH, Yun-Wei Cheng, Kuo-Cheng Lee, Chen-Ming Wu
  • INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME
    Publication number: 20230386964
    Abstract: In a method of forming a heat dissipating structure for a semiconductor chip, a soldering material is disposed on a top surface of the semiconductor chip. A first region of metal plating is formed on a surface of a lid. The first region has a first width and a first length. The first width is larger than a second width of the top surface of the semiconductor chip and the first length is larger than a second length of the top surface of the semiconductor chip. The lid is placed over the semiconductor chip so that the first region of metal plating of the lid is disposed over the soldering material to bond the lid to the semiconductor chip by a soldering material layer having an inverted trapezoidal shape between the lid and the top surface of the semiconductor chip.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Chang-Jung HSUEH, Yen Wei CHANG, Cheng-Nan LIN, Wei-Hung LIN, Ming-Da CHENG
  • SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME
    Publication number: 20230387239
    Abstract: A semiconductor device includes a substrate, a plurality of channel layers, two epitaxial structures, a conductive structure, a via, and a graphene barrier. The channel layers and the epitaxial structures are disposed over the substrate. The channel layers are connected between the epitaxial structures. The conductive structure is disposed on the substrate opposite to the epitaxial structures. The via is connected between one of the epitaxial structure and the conductive structure. The graphene barrier surrounds the via.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Yi YANG, Meng-Pei LU, Han-Tang HUNG, Ching-Fu YEH, Ming-Han LEE, Shau-Lin SHUE
  • Semiconductor Device and Method of Manufacture
    Publication number: 20230386926
    Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 30, 2023
    Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
  • Local Gate Height Tuning by CMP and Dummy Gate Design
    Publication number: 20230386927
    Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 30, 2023
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Keng-Yao Chen, Chen-Yu Tai, Yi-Ting Fu