Patents by Inventor Ming An

Ming An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11482952
    Abstract: A method for determining zero crossing occurrence in an alternating current (AC) signal with constant frequency of a permanent magnet synchronous motor (PMSM) includes: sampling the AC signal to obtain a plurality of data points; starting to count a number of consecutive data points that have sampled values with a same sign in a detection range, to generate a count value, wherein the consecutive data points are included in the plurality of data points; determining whether the count value is equal to a zero crossing determination value; and in response to the count value being equal to the zero crossing determination value, determining that a zero crossing occurs at a last data point of the consecutive data points.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: October 25, 2022
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Shih-Chieh Wang, Yong-Yi Jhuang, Ming-Fu Tsai
  • Patent number: 11482553
    Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes at least one pixel, and each pixel includes N subpixels, wherein each of the subpixels comprises a detection region, two first conductive contacts, wherein the detection region is between the two first conductive contacts, wherein N is a positive integer and is ?2.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: October 25, 2022
    Assignee: Artilux, Inc.
    Inventors: Szu-Lin Cheng, Chien-Yu Chen, Shu-Lu Chen, Yun-Chung Na, Ming-Jay Yang, Han-Din Liu, Che-Fu Liang
  • Patent number: 11480584
    Abstract: A system for biological analysis includes a housing, a block assembly within the housing having a sample block and a baseplate, a heated cover and a cover carrier. The sample block receives a sample holder comprising an RFID tag. A first drive mechanism generates relative movement between the sample block and the baseplate along a first axis. A second drive mechanism generates relative movement between the heated cover and the cover carrier along a second axis that is different from the first axis. Based on a first command the first drive mechanism releasably engages the sample block and operates the second drive mechanism to releasably engage the heated cover with the cover carrier. The system also includes first and second RFID antennas that receive RFID data from the sample holder RFID tag that is read by at least one RFID reader.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: October 25, 2022
    Assignees: LIFE TECHNOLOGIES HOLDINGS PTE LIMITED, LIFE TECHNOLOGIES CORPORATION
    Inventors: Kuan Moon Boo, Wei Fuh Teo, Zeqi Tan, Soo Yong Lau, Ming Tiong Sia, Woon Liang Soh, Ching Yee Lam, Shan Hua Dong, Marc Haberstroh, Michael C. Pallas, Hardeep Sangha
  • Patent number: 11483938
    Abstract: A method for connecting stacked circuit boards includes: a connecting structure is provided, the connecting structure is a bendable and flexible circuit board; a first circuit board and a plurality of supporting posts are provided, each of the supporting posts is dispersedly fixed to a side surface of the first circuit board; a second circuit board is provided, and two peripheral portions of the connecting structure are respectively fixed to the first circuit board and the second circuit board, the peripheral portions of the connecting structure are respectively near two opposite ends of the connecting structure; the connecting structure is bent to flip the second circuit board super-positioned above the first circuit board, and the second circuit board is connected to a free end of each of the supporting posts.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: October 25, 2022
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Rui-Wu Liu, Ming-Jaan Ho, Man-Zhi Peng
  • Patent number: 11480761
    Abstract: A six-piece optical image capturing system is disclosed. In order from an object side to an image side, the optical lens along the optical axis includes a first lens with refractive power; a second lens with refractive power; a third lens with refractive power; a fourth lens with refractive power; a fifth lens with refractive power, and a sixth lens with refractive power. At least one of the image-side surface and object-side surface of each of the six lens elements is aspheric. The optical lens of the optical image capturing system can increase aperture value and improve the imagining quality for use in compact cameras.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: October 25, 2022
    Assignee: Ability Opto-Electronics Technology Co., Ltd.
    Inventors: Yeong-Ming Chang, Chien-Hsun Lai, Yao-Wei Liu
  • Publication number: 20220336287
    Abstract: A method includes receiving a substrate having a front surface and a back surface; forming an isolation feature of a first dielectric material in the substrate, thereby defining an active region surrounded by the isolation feature; forming a gate stack on the active regions; forming a first and a second S/D feature on the fin active region; forming a front contact feature contacting the first S/D feature; thinning down the substrate from the back surface such that the isolation feature is exposed; selectively etching the active region, resulting in a trench surrounded by the isolation feature, the second S/D feature being exposed within the trench; forming, in the trench, a liner layer of a second dielectric material being different from the first dielectric material; forming a backside via feature landing on the second S/D feature within the trench; and forming a backside metal line landing on the backside via feature.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Li-Zhen Yu, Chia-Hao Chang, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220334910
    Abstract: A fabric connection assist system includes a networking device coupled to a fabric management system and a mobile device via a network. The networking device receives fabric connection information for its port from the fabric management system. When the mobile device subsequently identifies that port to the networking device, the networking device identifies fabric connection components to the mobile device that are indicated by the fabric connection information as being supported by its port. When the mobile device subsequently identifies a first of the fabric connection components to the networking device, and the networking device then detects that the first fabric connection component has been connected to its port, the networking device transmits a first fabric connection component confirmation communication to the mobile device that is configured to display a confirmation on the mobile device of the connection of the first fabric connection component to its port.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Inventors: Padmanabhan Narayanan, Ming Chung Chow, Ramar Nagaraj
  • Publication number: 20220336629
    Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung TSAI, Clement Hsingjen Wann, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More, Yu-Ming Lin
  • Publication number: 20220333410
    Abstract: In some examples, an apparatus can include a first locking member, the first locking member including a column, a first magnet movably located in the first locking member, a second locking member rotatably connected to the column, and a second magnet located in the second locking member, where when the first magnet is in a disengaged position, the second locking member is rotatable about the column, and when the first magnet is translated from the disengaged position to an engaged position in the first locking member, a magnetic force is created between the first magnet and the second magnet to align the first locking member and the second locking member.
    Type: Application
    Filed: April 19, 2021
    Publication date: October 20, 2022
    Inventors: Hou-Chu Su, Hsin-Yi Lee, Wei-Ming Tseng, Yu-Chen So
  • Publication number: 20220336393
    Abstract: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 20, 2022
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Ying-Ju Chen
  • Publication number: 20220336236
    Abstract: An apparatus includes a substrate stage configured to secure a substrate thereon and a motion mechanism configured to rotate the substrate stage. The substrate stage includes a plurality of holding pins for holding an edge of the substrate. Rotating the substrate stage causes a chemical solution dispensed on an upper surface of the substrate to spread outwardly toward the edge of the substrate. At least one of the plurality of holding pins includes at least one opening or at least one tapered side surface, or both, for guiding the chemical solution to flow off the substrate.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Chia-Lun Chen, Ming-Sung Hung, Po-Jen Shih, Wen-Hung Hsu
  • Publication number: 20220336233
    Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Chih-Ming Kuo, Lung-Hua Ho, You-Ming Hsu, Fei-Jain Wu
  • Publication number: 20220335192
    Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Inventors: Chia-Ping CHIANG, Ming-Hui CHIH, Chih-Wei HSU, Ping-Chieh WU, Ya-Ting CHANG, Tsung-Yu WANG, Wen-Li CHENG, Hui En YIN, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU
  • Publication number: 20220337214
    Abstract: A filter structure includes a ground plane in a first metal layer of an integrated circuit (IC) package, a plate in a second metal layer of the IC package, a dielectric layer between the ground plane and the plate, the ground plane, the dielectric layer, and the plate thereby being configured as a capacitive device, and an inductive device in a third metal layer of the IC package. The inductive device is electrically connected to the plate, and the plate and the inductive device are configured to have a resonance frequency greater than 1 GHz.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 20, 2022
    Inventor: Ming Hsien TSAI
  • Publication number: 20220337426
    Abstract: A digital key service device includes a casing, an input device, a data storage unit and a controlling unit. The input device is disposed near the casing or mounted on the casing, and configured to receive a user operation input. The data storage unit is disposed in the casing, and configured to store digital data and a digital key. The controlling unit is disposed in the casing, and configured to use the digital key to perform a digital key service or output the digital data to a host when authentication is complete. The authentication includes an operation verification procedure for verifying the user operation input. The authentication is complete when the controlling unit determines that the user operation input conforms to a preset timing-based input set.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 20, 2022
    Inventors: CHIA-HSIN CHENG, CHIH-PING HSIAO, MING-TING WU
  • Publication number: 20220335745
    Abstract: The present invention provides a display device, which includes a frame having an accommodating cavity and a display module disposed in the accommodating cavity. The display module includes a first light source, an optical unit, an imaging unit arranged on a side of the optical unit facing away from the first light source, and a lens array arranged on a side of the imaging unit facing away from the first light source. Corresponding to a preset pattern, light emitted by the first light source passes through the optical unit, the imaging unit and the lens array to form a default floating image in a floating display area outside the accommodating cavity. In addition, the present invention also provides a non-contact key and an input device including the above display module.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 20, 2022
    Inventors: YU JEN LAI, YA HAN KO, YU-MING HUANG, CHIA TSUN HUANG
  • Publication number: 20220333053
    Abstract: Embodiments of the invention relate to devices for assaying a biomolecule from a plant sample including: a microfluidic cartridge for assaying a biomolecule from a plant sample, including: a top layer; and a bottom layer spaced apart from the top layer in a generally parallel orientation with respect to the top layer, the bottom layer defining a plurality of wells therein that protrude from a surface of the bottom layer; and a filter module for filtering the plant sample, including a filter body defining: an upper portion including an inlet structure forming an inlet channel; and a bottom portion configured to accept and secure a filter membrane. The filter body is configured to accept a microvolume aliquot of the plant sample, the bottom structure includes an outlet structure forming an outlet channel on an outlet side of the filter membrane, and at least one of the plurality of wells includes an assay reagent solution.
    Type: Application
    Filed: September 10, 2020
    Publication date: October 20, 2022
    Applicants: The Johns Hopkins University, Pioneer Hi-Bred International, Inc.
    Inventors: Tza-Huei Wang, Dong Jin Shin, Fan-En Chen, Yue Yun, Arturo M. Escajeda, Ming X. Tan, Justin Schares, Blake Freml
  • Publication number: 20220335992
    Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung CHANG
  • Publication number: 20220336592
    Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Ting Fang, Chung-Hao Cai, Jui-Ping Lin, Chia-Hsien Yao, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220336289
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, and first and second gate structures on the fin structure. The first and second gate structures includes first and second interfacial oxide layers, respectively, first and second high-K gate dielectric layers disposed on the first and second TO layers, respectively, and first and second dopant control layers disposed on the first and second HK gate dielectric layers, respectively. The second dopant control layer has a silicon-to-metal atomic concentration ratio greater than an Si-to-metal atomic concentration ratio of the first dopant control layer. The semiconductor further includes first and second work function metal layers disposed on the first and second dopant control layers, respectively, and first and second gate metal fill layers disposed on the first and second work function metal layers, respectively.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Tien-Wei Yu