Abstract: This invention discloses a display panel including a first substrate, light emitting elements, a touch sensing structure and a conductive layer. The light emitting elements are disposed on the first substrate. The touch sensing structure is disposed on the first substrate and on a side away from a light emitting surface of the light emitting elements. The conductive layer is disposed between the light emitting elements and the first substrate and includes contacts or at least a portion of the touch sensing structure, and the light emitting elements and the contacts are electrically connected.

Abstract: The present invention relates to a driving method of a cholesteric liquid crystal display. It includes the steps in the following: driving each scan line by a dynamic driving scheme (DDS) including an Evolution phase; refreshing a frame of the cholesteric liquid crystal display by a full refresh mode, each scan line driven N times during the Evolution phase in the full refresh mode; and refreshing a part of the frame by a partial-refresh mode, each scan line driven M times in the Evolution phase in the partial-refresh mode, wherein M is greater than N.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.

Abstract: An image capturing unit includes an imaging element and a dual-shot injection-molded optical folding element that are adjacent to each other. The imaging element is configured for an imaging light to pass through. The dual-shot injection-molded optical folding element includes a first part and a second part. The first part is made of transparent material. The first part has a reflective surface configured to reflect the imaging light. The second part is made of opaque material, and the second part is fixed at periphery of the first part. The second part includes a supporting portion configured to support the dual-shot injection-molded optical folding element. The supporting portion maintains the dual-shot injection-molded optical folding element at a predetermined position corresponding to the imaging element through mechanism assembly.

Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

Abstract: A method of acquiring feature information of a detected object is provided, including: controlling the detected object to pass through a detection apparatus; controlling an imaging system to perform radiation scanning on the detected object acquiring a radiation scanning image of the detected object acquiring feature information of the detected object through the radiation scanning image. The detected object includes a first part, a detection part and a second part sequentially in a first direction. The acquiring feature information of the detected object through the radiation scanning image includes: acquiring a first boundary line between the detection part and the first part and a second boundary line between the detection part and the second part through the radiation scanning image; and calculating a dimension between the first boundary line and the second boundary line in the first direction to acquire a dimension of the detection part in the first direction.

Abstract: A light-emitting diode and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, an LED wafer is provided. The LED wafer includes a substrate and a light-emitting semiconductor stacking structure positioned on the surface of the substrate. The light-emitting semiconductor stacking structure includes a first type semiconductor layer, an active layer, and a second type semiconductor layer from a side of the substrate. Second, dicing lanes are defined on the upper surface of the LED wafer. Third, dicing is performed along the dicing lanes of the substrate using a laser. The laser is focused on the lower surface of the substrate to form a surface hole and focused inside the substrate to form an internal hole. The diameter of the surface hole is greater than the diameter of the internal hole. Fourth, the LED wafer is separated into LED chips along the dicing lanes.

Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: The present disclosure provides a cryptocurrency securing system and a cryptocurrency securing method thereof. The system receives a cryptocurrency transaction information from a user device, and determines whether a policy data corresponding to the cryptocurrency transaction information is legal. When the policy data corresponding to the cryptocurrency transaction information is legal, the system derives a cryptocurrency private key information via a personal identification number of the user device. The system then encrypts the cryptocurrency transaction information via the cryptocurrency private key information for deriving an encrypted cryptocurrency transaction information, and broadcasts the encrypted cryptocurrency transaction information to a blockchain network.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.

Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Abstract: An organic optoelectronic device comprises a first electrode, an active layer and a second electrode. Active layer materials of the active layer comprise a block conjugated polymer materials which includes a structure of formula I: The polymer 1 is a p-type polymer with high energy gap, and the polymer 1 comprises a first electron donor and a first electron acceptor arranged alternately. The polymer 2 is a p-type polymer with low energy gap, and the polymer 2 comprises a second electron donor and a second electron acceptor arranged alternately. Wherein, o and p>0. The organic optoelectronic device of the present invention transfers carriers through the polymer 2 with low energy gap, and suppresses the recombination probability of carriers through the polymer 1 with high energy gap, thereby reducing the leakage current of the organic optoelectronic device.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.