Patents by Inventor Ming-Che Ho
Ming-Che Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230065788Abstract: Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chung Chang, Ming-Che Ho, Hung-Jui Kuo
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Publication number: 20230069737Abstract: A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. The routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. The semiconductor die is electrically connected to the routing via. Along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chung Chang, Ming-Che Ho, Hung-Jui Kuo
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Patent number: 11594484Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.Type: GrantFiled: June 29, 2020Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky, Ming-Che Ho, Yi-Wen Wu, Ching-Hui Chen, Kuo-Chio Liu
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Publication number: 20230052776Abstract: A manufacturing method of a semiconductor package includes the following steps. An integrated circuit structure is provided, wherein the integrated circuit structure includes an integrated circuit and a metallization layer covering a back surface of the integrated circuit. An encapsulation material is provided to laterally encapsulate the integrated circuit structure. A redistribution structure is provided over the integrated circuit structure and the encapsulation material, wherein the redistribution structure includes a thermal metal layer furthermost from the integrated circuit structure, wherein the thermal metal layer is thermally coupled to the metallization layer. A solder layer is provided over the thermal metal layer, wherein the solder layer is thermally coupled to the thermal metal layer.Type: ApplicationFiled: November 2, 2022Publication date: February 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho
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Publication number: 20230018511Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
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Patent number: 11545457Abstract: A semiconductor package, a redistribution structure and a method for forming the same are provided. The redistribution structure for coupling an encapsulated die is provided, the redistribution structure includes a conductive pattern disposed over and electrically coupled to the encapsulated die. The conductive pattern extends beyond an edge of the encapsulated die along a first extending direction which intersects a second extending direction of the edge of the encapsulated die by an angle in a top view, and an impurity concentration of sulfur in the conductive pattern is less than about 0.1 ppm.Type: GrantFiled: August 30, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiang-Hao Lee, Hung-Jui Kuo, Ming-Che Ho
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Patent number: 11495507Abstract: A manufacturing method of a semiconductor package including the following steps is provided. A redistribution structure is formed over an encapsulated semiconductor device carried by a carrier, wherein the redistribution structure includes an organic polymer layer and a redistribution circuit layer electrically connected to the semiconductor device. An inorganic protection layer is formed to entirely cover an upper surface of the redistribution structure, wherein an oxygen and/or water vapor permeability of the inorganic protection layer is substantially lower than an oxygen and/or vapor permeability of the organic polymer layer. An adhesive is formed on the inorganic protection layer. An insulating cover is adhered on the inorganic protection layer through the adhesive.Type: GrantFiled: June 10, 2021Date of Patent: November 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho, Chia-Hung Liu
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Patent number: 11495506Abstract: A semiconductor package includes a first integrated circuit structure, a first encapsulation material laterally encapsulating the first integrated circuit structure, a first redistribution structure, a solder layer, a second integrated circuit structure, a second encapsulation material second laterally encapsulating the second integrated circuit structure and a second redistribution structure. The first integrated circuit structure includes a first metallization layer. The first redistribution structure is disposed over the first integrated circuit structure and first encapsulation material. The first metallization layer faces away from the first redistribution structure and thermally coupled to the first redistribution structure. The solder layer is dispose over the first redistribution structure. The second integrated circuit structure is disposed on the first redistribution structure and includes a second metallization layer in contact with the solder layer.Type: GrantFiled: March 30, 2020Date of Patent: November 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho
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Publication number: 20220352046Abstract: A semiconductor package includes a first integrated circuit, a first passivation layer, a second passivation layer, a thermal pattern, an adhesive layer and a second integrated circuit. The first integrated circuit is encapsulated by an encapsulant. The first passivation layer is disposed over the first integrated circuit and the encapsulant. The second passivation layer is disposed over the first passivation layer. The thermal pattern is disposed in the first passivation layer and the second passivation layer. The adhesive layer is disposed over the second passivation layer and in direct contact with the thermal pattern. The second integrated circuit is adhered to the first integrated circuit through the adhesive layer.Type: ApplicationFiled: April 28, 2021Publication date: November 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho
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Publication number: 20220336376Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die; and a redistribution structure including: a plurality of dielectric layers over the encapsulant and the integrated circuit die; a plurality of metallization patterns in the dielectric layers, the metallization patterns being electrically coupled to the integrated circuit die; and a sealing ring in the dielectric layers, the sealing ring extending around the metallization patterns, the sealing ring being electrically isolated from the metallization patterns and the integrated circuit die, the sealing ring including a plurality of sealing ring layers, each of the sealing ring layers including a via portion extending through a respective one of the dielectric layers, the via portion of each of the sealing ring layers being aligned along a same common axis.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Chen-Hua Yu, Tzu Yun Huang, Ming-Che Ho, Hung-Jui Kuo
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Publication number: 20220328386Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Chen-Hua Yu, Hung-Jui Kuo, Ming-Che Ho, Tzung-Hui Lee
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Publication number: 20220310519Abstract: Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Che Ho, Hung-Jui Kuo, Tzung-Hui Lee
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Patent number: 11410953Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.Type: GrantFiled: August 3, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu
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Patent number: 11410918Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.Type: GrantFiled: February 28, 2018Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Hung-Jui Kuo, Ming-Che Ho, Tzung-Hui Lee
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Patent number: 11398416Abstract: A structure including a semiconductor die, a conductive pillar, and an insulating encapsulation is provided. The conductive pillar includes a first pillar portion and a second pillar portion disposed on the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. The insulating encapsulation laterally encapsulates the semiconductor die and the conductive pillar.Type: GrantFiled: November 28, 2019Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzung-Hui Lee, Hung-Jui Kuo, Ming-Che Ho
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Patent number: 11393763Abstract: Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.Type: GrantFiled: May 28, 2020Date of Patent: July 19, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Che Ho, Hung-Jui Kuo, Tzung-Hui Lee
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Patent number: 11387191Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die; and a redistribution structure including: a plurality of dielectric layers over the encapsulant and the integrated circuit die; a plurality of metallization patterns in the dielectric layers, the metallization patterns being electrically coupled to the integrated circuit die; and a sealing ring in the dielectric layers, the sealing ring extending around the metallization patterns, the sealing ring being electrically isolated from the metallization patterns and the integrated circuit die, the sealing ring including a plurality of sealing ring layers, each of the sealing ring layers including a via portion extending through a respective one of the dielectric layers, the via portion of each of the sealing ring layers being aligned along a same common axis.Type: GrantFiled: July 18, 2019Date of Patent: July 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Tzu Yun Huang, Ming-Che Ho, Hung-Jui Kuo
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Patent number: 11289410Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.Type: GrantFiled: September 17, 2019Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hung-Jui Kuo, Ming-Che Ho, Tzung-Hui Lee
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Publication number: 20220068869Abstract: A semiconductor package, a redistribution structure and a method for forming the same are provided. The redistribution structure for coupling an encapsulated die is provided, the redistribution structure includes a conductive pattern disposed over and electrically coupled to the encapsulated die. The conductive pattern extends beyond an edge of the encapsulated die along a first extending direction which intersects a second extending direction of the edge of the encapsulated die by an angle in a top view, and an impurity concentration of sulfur in the conductive pattern is less than about 0.1 ppm.Type: ApplicationFiled: August 30, 2020Publication date: March 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiang-Hao Lee, Hung-Jui Kuo, Ming-Che Ho
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Patent number: 11239233Abstract: An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.Type: GrantFiled: September 5, 2019Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Hung-Jui Kuo, Ming-Che Ho