Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a dielectric layer, a first redistribution layer (RDL) and a second RDL. The encapsulant laterally encapsulates the die. The dielectric layer is located on the encapsulant and the die. The first RDL penetrates through the dielectric layer to connect to the die. The second RDL is located on the first RDL and the dielectric layer. The second RDL and the first RDL share a common seed layer.

Abstract: A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.

Abstract: Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.

Abstract: A manufacturing method of a semiconductor package including the following steps is provided. A redistribution structure is formed over an encapsulated semiconductor device carried by a carrier, wherein the redistribution structure includes an organic polymer layer and a redistribution circuit layer electrically connected to the semiconductor device. An inorganic protection layer is formed to entirely cover an upper surface of the redistribution structure, wherein an oxygen and/or water vapor permeability of the inorganic protection layer is substantially lower than an oxygen and/or vapor permeability of the organic polymer layer. An adhesive is formed on the inorganic protection layer. An insulating cover is adhered on the inorganic protection layer through the adhesive.

Abstract: A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.

Abstract: A semiconductor package includes a first integrated circuit structure, a first encapsulation material laterally encapsulating the first integrated circuit structure, a first redistribution structure, a solder layer, a second integrated circuit structure, a second encapsulation material second laterally encapsulating the second integrated circuit structure and a second redistribution structure. The first integrated circuit structure includes a first metallization layer. The first redistribution structure is disposed over the first integrated circuit structure and first encapsulation material. The first metallization layer faces away from the first redistribution structure and thermally coupled to the first redistribution structure. The solder layer is dispose over the first redistribution structure. The second integrated circuit structure is disposed on the first redistribution structure and includes a second metallization layer in contact with the solder layer.

Abstract: In an embodiment, a device includes: an integrated circuit die; a through via adjacent the integrated circuit die; a molding compound encapsulating the integrated circuit die and the through via; and a redistribution structure including: a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line.

Abstract: A semiconductor package and a method of forming the same are disclosed. A method of forming a semiconductor package includes the following operations. A polymer layer is formed over a die. A metal feature is formed in the polymer layer. An argon-containing plasma treatment is performed to the polymer layer and the metal feature.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A semiconductor package includes an encapsulated semiconductor device, a redistribution structure, and a protection layer. The encapsulated semiconductor device includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. The redistribution structure is disposed on the encapsulated semiconductor device and includes a dielectric layer and a redistribution circuit layer electrically connected to the semiconductor device. The protection layer at least covers the dielectric layer, wherein an oxygen permeability or a water vapor permeability of the protection layer is substantially lower than an oxygen permeability or a vapor permeability of the dielectric layer.

Abstract: Provided is a package structure including a die; an electrically connecting structure having a die attach region and a peripheral region surrounding the die attach region, wherein the die is disposed on the electrically connecting structure within the die attach region; an insulating protrusion disposed in the peripheral region and extending in a thickness direction of the die; a conductive structure disposed on the electrically connecting structure and encapsulating the insulating protrusion, wherein the conductive structure is electrically coupled to the electrically connecting structure and the die; and a dielectric structure disposed on the electrically connecting structure and encapsulating the die and the conductive structure.

Abstract: In an embodiment, a device includes: an integrated circuit die; a through via adjacent the integrated circuit die; a molding compound encapsulating the integrated circuit die and the through via; and a redistribution structure including: a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line.

Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first dielectric layer, a first conductive pattern and a barrier layer. The first conductive pattern is disposed in a second dielectric layer over the first dielectric layer. The barrier layer is disposed at an interface between the first conductive pattern and the second dielectric layer and an interface between the first dielectric layer and the second dielectric layer.

Abstract: A method, an image processing device, and a system for generating a disparity map are proposed. The method includes the following steps. Images of a specific scene are captured by two image sensors to generate two original images. A shrinking process is performed on the two original images to generate two shrunk images. A shrunk disparity map is generated by using the two shrunk images. A magnifying process is performed on the shrunk disparity map to generate a magnified disparity map. Whether each magnified disparity value of the magnified disparity map is reliable is determined so as to accordingly generate a refined disparity map.

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.

Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.

Abstract: A semiconductor package and a method of forming the same are disclosed. A method of forming a semiconductor package includes the following operations. A polymer layer is formed over a die. A metal feature is formed in the polymer layer. An argon-containing plasma treatment is performed to the polymer layer and the metal feature.

Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

Abstract: A structure including a semiconductor die, a conductive pillar, and an insulating encapsulation is provided. The conductive pillar includes a first pillar portion and a second pillar portion disposed on the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. The insulating encapsulation laterally encapsulates the semiconductor die and the conductive pillar.

Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a metallization layer and a dielectric layer disposed on the metallization layer. The metallization layer has conductive patterns, where each of the conductive patterns includes crystal grains, the crystal grains each are in a column shape and include a plurality of first banded structures having copper atoms oriented on a (220) lattice plane.