Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.

Abstract: An optoelectronic module includes an interposer base having first and second recesses formed on a specified surface thereof; a joint material layer filled in the first and second recesses; a first optoelectronic element placed in the first recess and coupled to the interposer base via the joint material layer, wherein an optical signal is emitted from or passes through a lateral surface of the first optoelectronic element; and a second optoelectronic element placed in the second recess and coupled to the interposer base via the joint material layer, wherein a lateral surface of the second optoelectronic element faces the lateral surface of the first optoelectronic element for coupling to and receiving the optical signal emitted from or passing through the lateral surface of the first optoelectronic element. A fixture is used to place the first and second optoelectronic elements into the first and second recesses while controlling some critical distances.

Abstract: The method of a wafer level packaging includes preparing a substrate, assembling a system on a first side of the substrate, and placing solder balls on a second side of the substrate. The soldering balls s fixed on to the second side of the substrate after the module has been assembled.

Abstract: A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p? region of the body. The TFT may have an n+ source and an n+ drain on either side of the p? region of the body. Thus, the TFT has an n+/p?/n+/p?/n+ structure in this example. The n+ layer in the p? region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p? body and/or thickness of the n+ layer in the p? body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n? region of the body. The TFT may have a p+ source and a p+ drain on either side of the p? region of the body.

Abstract: An optoelectronic module includes an interposer base having first and second recesses formed on a specified surface thereof; a joint material layer filled in the first and second recesses; a first optoelectronic element placed in the first recess and coupled to the interposer base via the joint material layer, wherein an optical signal is emitted from or passes through a lateral surface of the first optoelectronic element; and a second optoelectronic element placed in the second recess and coupled to the interposer base via the joint material layer, wherein a lateral surface of the second optoelectronic element faces the lateral surface of the first optoelectronic element for coupling to and receiving the optical signal emitted from or passing through the lateral surface of the first optoelectronic element. A fixture is used to place the first and second optoelectronic elements into the first and second recesses while controlling some critical distances.

Abstract: An electronic module having an electromagnetic shielding structure and its manufacturing method are provided. At first, a first substrate and a second substrate are separately provided. At least one electronic element and at least one connection pad are formed on a surface of the first substrate. The second substrate includes a conductive film and at least one conductive bump is formed on a surface of the conductive film. The first substrate and the second substrate are laminated together wherein the conductive bump is aligned with and connected to the connection pad to obtain the electronic module.

Abstract: A semiconductor package includes a substrate having a front side, a bottom side, and a sidewall along a perimeter of the substrate, a plurality of solder pads on the bottom side, at least one EM shielding contact structure on the bottom side and partially exposed on the sidewall, a semiconductor device mounted on the front side, a mold compound on the front side and covering the semiconductor device, and an EM shielding layer conformally covering the mold compound and the sidewall. The EM shielding layer is in direct contact with the exposed portion of the EM shielding contact structure on the sidewall.

Abstract: A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p? region of the body. The TFT may have an n+ source and an n+ drain on either side of the p? region of the body. Thus, the TFT has an n+/p?/n+/p?/n+ structure in this example. The n+ layer in the p? region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p? body and/or thickness of the n+ layer in the p? body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n? region of the body. The TFT may have a p+ source and a p+ drain on either side of the p? region of the body.

Abstract: Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that includes forming a first set of trenches by etching a first set of oxide pillars to a first depth and forming a second set of trenches by etching a second set of oxide pillars to a second depth higher than the first depth, forming a first set of gate structures within the first set of trenches, forming a second set of gate structures within the second set of trenches, performing a second etching process that includes forming a third set of trenches by etching the first set of gate structures from a second initial depth to a third depth and forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth.

Abstract: Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that includes forming a first set of trenches by etching a first set of oxide pillars to a first depth and forming a second set of trenches by etching a second set of oxide pillars to a second depth higher than the first depth, forming a first set of gate structures within the first set of trenches, forming a second set of gate structures within the second set of trenches, performing a second etching process that includes forming a third set of trenches by etching the first set of gate structures from a second initial depth to a third depth and forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth.

Abstract: A chip level EMI shielding structure and manufacture method thereof are provided. The chip level EMI shielding structure includes a semiconductor substrate, at least one ground conductor line, a ground layer, and a connection structure. The ground conductor line is disposed on a first surface of the semiconductor substrate, and the ground layer is disposed on a second surface of the semiconductor substrate. The connection structure is formed on a lateral wall of the semiconductor substrate for connecting the ground conductor lines with the ground layer to form a shielding. With such arrangement, the chip level EMI shielding structure can reduce the chip size and the manufacturing cost.

Abstract: A semiconductor package includes a substrate having a front side, a bottom side, and a sidewall along a perimeter of the substrate, a plurality of solder pads on the bottom side, at least one EM shielding contact structure on the bottom side and partially exposed on the sidewall, a semiconductor device mounted on the front side, a mold compound on the front side and covering the semiconductor device, and an EM shielding layer conformally covering the mold compound and the sidewall. The EM shielding layer is in direct contact with the exposed portion of the EM shielding contact structure on the sidewall.

Abstract: A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess.

Abstract: A vertically oriented thin film transistor (TFT) having a tunnel barrier is disclosed. The tunnel barrier may be formed from a dielectric such as silicon oxide or hafnium oxide. The vertically oriented TFT selection device with tunnel barrier may serve as a selection device in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a global bit line to/from a vertical bit line in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a source line to/from a channel of a vertical NAND string in a 3D memory array. A vertical TFT with tunnel barrier has a high breakdown voltage, low leakage current, and high on current. The tunnel barrier can be at the top junction or bottom junction of the TFT.

Abstract: A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess.

Abstract: A tungsten-filament-like LED lamp structure includes a lamp shade, a heat dissipating frame, a lamp holder, a LED substrate, a LED light source and a light spreader assembly. The light spreader assembly includes a reflective device and a diverging element, wherein light rays transmitting through a light-permeable portion of the reflective device are diverged by the diverging element to generate frontward lighting, and reflective surfaces of the reflective device control the reflected light rays to generate sideward lighting and backward lighting and thus generate an optical field similar to that of a conventional tungsten filament lamp. Thus, the properties of energy saving, vibration resistant and long lifetime better than those of the conventional lamp can be achieved, and the invention can be directly applied to the conventional lamp structure to decrease the production and maintenance costs.

Abstract: An earthquake warning disaster prevention and safety report-back system comprises a servo host group constituted by servo hosts and a mobile communication device. When an earthquake is formed, the servo hosts that are distributed by location in Taiwan are utilized for simultaneously receiving earthquake real-time data information transmitted from the Central Weather Bureau, using the servo hosts to evaluate a physical location of a client, and using one servo host that is located at an optimum (nearest) site to distributively transmit earthquake real-time data information to the mobile communication device of the client. When the mobile communication device receives the earthquake information, the mobile communication device transmits a warning message to the client and provides earthquake magnitude and an earthquake wave arrival time of the physical location as instructions to perform prevention and escape measures, thereby seizing the recuse golden hour.

Abstract: A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.

Abstract: A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.

Abstract: An electromagnetic interference (EMI) shielding structure, which includes: a substrate, at least one chip unit, a packing layer, and an EMI shielding unit. The chip unit is disposed on the surface of the substrate and electrically coupled thereto. The packing layer is formed on the substrate and covers the chip unit. The EMI shielding unit includes: a first, second, and third shielding layer. The first shielding layer covers the outer surface of the packing layer and the lateral surface of the substrate. The second and third shielding layer respectively covers the outer surface of the first and second shielding layer. Based on the instant disclosure, the EMI shielding unit uses the methods of sputtering and electroless plating, to increase the adhesion strength of the EMI shielding unit and make the thickness of the shielding layer uniform. The instant disclosure raises the EMI shielding efficiency and lowers the manufacturing cost.