Abstract: A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.

Abstract: An electromagnetic interference (EMI) shielding structure, which includes: a substrate, at least one chip unit, a packing layer, and an EMI shielding unit. The chip unit is disposed on the surface of the substrate and electrically coupled thereto. The packing layer is formed on the substrate and covers the chip unit. The EMI shielding unit includes: a first, second, and third shielding layer. The first shielding layer covers the outer surface of the packing layer and the lateral surface of the substrate. The second and third shielding layer respectively covers the outer surface of the first and second shielding layer. Based on the instant disclosure, the EMI shielding unit uses the methods of sputtering and electroless plating, to increase the adhesion strength of the EMI shielding unit and make the thickness of the shielding layer uniform. The instant disclosure raises the EMI shielding efficiency and lowers the manufacturing cost.

Abstract: A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess.

Abstract: A chip stacked structure and method of fabricating the same are provided. The chip stacked structure includes a first chip and a second chip stacked on the first chip. The first chip has a plurality of metal pads disposed on an upper surface thereof and grooves disposed on a side surface thereof. The metal pads are correspondingly connected to upper openings of the grooves. The second chip has a plurality of grooves on a side surface of the second chip, locations of which are corresponding to that of the grooves on the side surface of the first chip. Conductive films are formed on the grooves of the first chip and the second chip and the metal pads to electronically connect the first chip and second chip. The chip stacked structure may simplify the process and improve the process yield rate.

Abstract: A multi-wavelength light-emitting module that includes a PCB, a drive IC structure, a conductive structure, a multi-wavelength LED array set, a plurality of conductive elements, and an optical amplifier structure. The PCB has at least one input/output pad. The drive IC structure is disposed on the PCB and having at least one concave groove formed on top surface thereof. The conductive structure is electrically connected between the drive IC structure and the at least one input/output pad. The multi-wavelength LED array set is received in the at least one concave groove. The conductive elements are electrically connected between drive IC structure and the multi-wavelength LED array set, respectively. The optical amplifier structure is disposed over the multi-wavelength LED array set for receiving light sources from the multi-wavelength LED array set.

Abstract: An electromagnetic interference (EMI) shielding structure for integrated circuit (IC) substrate includes a plurality of conductive contacts, a covering layer, and a sputtered layer. The conductive contacts are formed at the perimeter of a chip area on the IC substrate. The covering layer is formed on the conductive contacts and covers the chip area. A groove is formed on the covering layer for exposing the conductive contacts. The sputtered layer is formed on the covering layer and connected to the conductive contacts. The EMI shielding structure can restrain the interference in the chip area.

Abstract: A miniaturized electromagnetic interference (EMI) shielding structure is disclosed, which includes a substrate and a plurality of chip modules disposed thereon. The substrate has a plurality of ground portions formed thereon. Each chip module includes: at least one chip unit disposed on the substrate and connected electrically thereto; at least one conductive bump disposed on the substrate adjacent to the chip unit and connected electrically to the corresponding ground portion; an encapsulation layer arranged on the substrate and covers the chip unit and the conductive bump; and an EMI shielding layer covering the encapsulation layer and electrically connected with an exposed surface of the conductive bump, to allow the EMI shielding layer be electrically connected to the ground portion. The disclosure of the present invention allows each chip module to have its own EMI shielding capability.

Abstract: A wafer-level electromagnetic interference (EMI) shielding structure, which includes: a wafer, an exposed circuit unit, and an EMI shielding unit. The exposed circuit unit is disposed on the top surface of the wafer. At least one conductor is disposed on the exposed circuit unit. The EMI shielding unit has a first EMI shielding layer set around the surrounding surface of the wafer, and a second EMI shielding layer coated to the bottom surface of the wafer. Based on the wafer-level manufacturing process of the instant disclosure, the EMI shielding structure is miniaturized, and each individual wafer is protected against the EMI effect.

Abstract: An electromagnetic interference (EMI) shielding structure, which includes: a substrate, at least one chip unit, a packing layer, and an EMI shielding unit. The chip unit is disposed on the surface of the substrate and electrically coupled thereto. The packing layer is formed on the substrate and covers the chip unit. The EMI shielding unit includes: a first, second, and third shielding layer. The first shielding layer covers the outer surface of the packing layer and the lateral surface of the substrate. The second and third shielding layer respectively covers the outer surface of the first and second shielding layer. Based on the instant disclosure, the EMI shielding unit uses the methods of sputtering and electroless plating, to increase the adhesion strength of the EMI shielding unit and make the thickness of the shielding layer uniform. The instant disclosure raises the EMI shielding efficiency and lowers the manufacturing cost.

Abstract: A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.

Abstract: A chip level EMI shielding structure and manufacture method thereof are provided. The chip level EMI shielding structure includes a semiconductor substrate, at least one ground conductor line, a ground layer, and a connection structure. The ground conductor line is disposed on a first surface of the semiconductor substrate, and the ground layer is disposed on a second surface of the semiconductor substrate. The connection structure is formed on a lateral wall of the semiconductor substrate for connecting the ground conductor lines with the ground layer to form a shielding. With such arrangement, the chip level EMI shielding structure can reduce the chip size and the manufacturing cost.

Abstract: A chip stacked structure and method of fabricating the same are provided. The chip stacked structure includes a first chip and a second chip stacked on the first chip. The first chip has a plurality of metal pads disposed on an upper surface thereof and grooves disposed on a side surface thereof. The metal pads are correspondingly connected to upper openings of the grooves. The second chip has a plurality of grooves on a side surface of the second chip, locations of which are corresponding to that of the grooves on the side surface of the first chip. Conductive films are formed on the grooves of the first chip and the second chip and the metal pads to electronically connect the first chip and second chip. The chip stacked structure may simplify the process and improve the process yield rate.

Abstract: An easy curtain structure contains a curtain piece formed in a continuous curve and concave shape, allowing to be folded, including a plurality of bores disposed on a number of raised folding ribs thereof respectively in a cross arrangement, and including at least one positioning structure mounted on a top and a bottom ends thereof respectively so as to be expended and to be fixed by using the positioning structure, wherein the positioning structure includes at lease one sucker fixed on the top and the bottom ends of the curtain piece, thereby the sunshine is stopped to directly shine indoors by the continuously curved and concaved curtain piece or through the bores to obtain heatproof, anti-sun, and bright effect.

Abstract: A projection apparatus includes an illuminating unit, an imaging unit, a lens unit, and a control unit. The illuminating unit includes a light source, and a light source driving module operable to drive the light source to provide an illumination beam. The imaging unit is operable so as to modulate the illumination beam into an image beam. The lens unit is disposed on an optical path of the image beam for projecting the image beam. The control unit is coupled electrically to the illuminating unit and the imaging unit. The control unit is configured to execute an activating thread for initializing the imaging unit after controlling initial driving of the light source by the light source driving module, and a monitoring thread for monitoring the light source driving module for a success signal that indicates successful provision of the illumination beam by the light source.

Abstract: An embedded package structure module with high-density electrical connections, including: a drive IC structure, an LED array structure and a plurality of conductive structures. The drive IC structure has at least one concave groove. The LED array structure is received in the at least one concave groove of the drive IC structure, and the LED array structure has a plurality of second open grooves formed on its lateral wall and close to the drive IC structure. The conductive structures respectively traverse the second open grooves in order to make the conductive structures electrically connect between the drive IC structure and the LED array structure.

Abstract: A multi-wavelength light-emitting module with high density electrical connections includes a drive IC structure and a multi-wavelength LED array structure. The drive IC structure has a drive IC unit formed on a top surface thereof. The multi-wavelength LED array structure is disposed on the top surface of the drive IC structure, and the multi-wavelength LED array structure has a conductive trace unit formed on an outer surface thereof and electrically connected to the drive IC unit.

Abstract: A method for packaging a multi-wavelength LED array package module includes: forming at least one concave groove on a drive IC structure; arranging a multi-wavelength LED array set in the at least one concave groove; solidifying a plurality of liquid conductive materials to form a plurality of conductive elements that is electrically connected between the drive IC structure and the multi-wavelength LED array set by a printing, a coating, a stamping, or a stencil printing process; arranging the drive IC structure on a PCB with at least one input/output pad; and then forming a conductive structure that is electrically connected between the drive IC structure and the at least one input/output pad.

Abstract: An embedded package structure module with high-density electrical connections, including: a drive IC structure, an LED array structure and a plurality of conductive structures. The drive IC structure has at least one concave groove. The LED array structure is received in the at least one concave groove of the drive IC structure, and the LED array structure has a plurality of second open grooves formed on its lateral wall and close to the drive IC structure. The conductive structures respectively traverse the second open grooves in order to make the conductive structures electrically connect between the drive IC structure and the LED array structure.

Abstract: A method for rapidly identifying a point mutation in porcine insulin-like-growth factor 2 intron 7 uses published primers to amplify the target DNA fragments by polymerase chain reaction. The DNA fragments are cloned and sequenced for confirmation and method validation. The key positions of the sequence are modified to generate three primers for amplifying different DNA fragments with different genotypes by PCR to avoid additional restriction enzyme digestion. A long primer is used to specifically amplify the lean muscle mass-enhancing allele, a short primer is used to specifically amplify the lean muscle mass-suppressing allele, and the third primer is shared and anneals to the complementary strand. After PCR and electrophoresis, samples with only the 92 bp band are identified as the CC genotype, samples with only the 72 bp band are identified as the GG genotype, and samples with both 92 bp and 72 bp bands are identified as heterozygotes.

Abstract: A method for arranging print head chips, includes: (a) setting a first fiducial mark and a second fiducial mark on a PCB for determining coordinate positions of a plurality of array units that are arranged on the PCB and calculating a print range of the array units, wherein each array unit has a plurality of spots that are transversely arranged from the first one of the spots to the last one of the spots in sequence; (b) setting a third fiducial mark as a start point for arranging the first spot of a first array unit of the array units on the PCB; and (c) arranging other array units on the PCB in sequence according to the coordinate positions and the start point.