Patents by Inventor Ming Chen

Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230027552
    Abstract: A fluid immersion cooling system includes a fluid tank that contains a layer of a dual-phase coolant fluid and one or more layers of single-phase coolant fluids. The dual-phase and single-phase coolant fluids are immiscible, with the dual-phase coolant fluid having a lower boiling point and higher density than a single-phase coolant fluid. A substrate of an electronic system is submerged in the tank such that high heat-generating components are immersed at least in the layer of the dual-phase coolant fluid. Heat from the components is dissipated to the dual-phase coolant fluid to generate vapor bubbles of the dual-phase coolant fluid. The vapor bubbles rise to a layer of a single-phase coolant fluid that is above the layer of the dual-phase coolant fluid. The vapor bubbles condense to droplets of the dual-phase coolant fluid. The droplets fall down into the layer of the dual-phase coolant fluid.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 26, 2023
    Applicant: Super Micro Computer, Inc.
    Inventors: Yueh Ming LIU, Yu Hsiang HUANG, Yu Chuan CHANG, Tan Hsin CHANG, Hsiao Chung CHEN, Chia-Wei CHEN, Chih-Ta CHEN, Cheng-Hung LIN, Ming-Te HSU
  • Publication number: 20230028676
    Abstract: Systems and methods for determining fiber optic facility (cable) location using distributed fiber optic sensing (DFOS) and sequence pattern matching of vibration excitation signals applied to a sensor fiber. The use of sequence pattern matching with unique pattern codes allow for the precise determination of location and length of deployed fiber cable while exhibiting an immunity from environmental vibrations proximate to the fiber. As a result improved measurements are realized and false alarms are eliminated.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 26, 2023
    Applicant: NEC LABORATORIES AMERICA, INC
    Inventors: Ming-Fang HUANG, Shaobo HAN, Ting WANG, Yuheng CHEN, Yangmin DING, Yue TIAN, Sarper OZHARAR
  • Publication number: 20230027768
    Abstract: A computing method for performing a matrix multiplying-and-accumulating computation by a flash memory array which includes word lines, bit lines and flash memory cells. The computing method includes the following steps: respectively storing a weight value in each of the flash memory cells, receiving a plurality of input voltages via the word lines, performing an computation on one of the input voltages and the weight value by each of the flash memory cells to obtain an output current, outputting the output currents of the flash memory cells via the bit lines, and accumulating the output currents of the flash memory cells connected to the same bit line of the bit lines to obtain a total output current. Each of the flash memory cells is an analog device, and each of the input voltages, each of the output currents and each of the weight values are analog values.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 26, 2023
    Inventors: Chung-Chieh CHEN, Da-Ming CHIANG, Shuo-Hong HUNG
  • Publication number: 20230026918
    Abstract: A method for handling a Random Access (RA) procedure in a Bandwidth Part (BWP) switching operation is provided. The method includes: receiving a configuration of a first BWP through Radio Resource Control (RRC) signaling from a Base Station (BS); initiating an RA procedure on the first BWP; receiving, during the RA procedure on the first BWP, Downlink Control Information (DCI) indicating a BWP switching from the first BWP to a second BWP; determining whether to switch to the second BWP in response to receiving the DCI; and in a case that the UE determines to switch to the second BWP: stopping the RA procedure that is ongoing on the first BWP; determining, after stopping the RA procedure, whether the second BWP is configured with an RA resource; and initiating, after determining that the second BWP is not configured with the RA resource, a new RA procedure on an initial BWP.
    Type: Application
    Filed: September 30, 2022
    Publication date: January 26, 2023
    Inventors: HUNG-CHEN CHEN, CHIE-MING CHOU, CHIA-HUNG WEI, YUNG-LAN TSENG
  • Publication number: 20230024339
    Abstract: A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.
    Type: Application
    Filed: February 9, 2022
    Publication date: January 26, 2023
    Inventors: Chih-Hsuan Cheng, Chieh-Fang Chen, Sheng-Chen Wang, Chieh-Yi Shen, Han-Jong Chia, Feng-Ching Chu, Meng-Han Lin, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20230028802
    Abstract: This disclosure provides a lens assembly that has an optical path and includes a lens element and a light-blocking membrane layer. The lens element has an optical portion, and the optical path passes through the optical portion. The light-blocking membrane layer is coated on the lens element and adjacent to the optical portion. The light-blocking membrane layer has a distal side and a proximal side that is located closer to the optical portion than the distal side. The proximal side includes two extension structures and a recessed structure. Each of the extension structures extends along a direction away from the distal side, and the extension structures are not overlapped with each other in a direction in parallel with the optical path. The recessed structure is connected to the extension structures and recessed along a direction towards the distal side.
    Type: Application
    Filed: November 10, 2021
    Publication date: January 26, 2023
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Jyun-Jia CHENG, Yu Chen LAI, Ming-Ta CHOU, Cheng-Feng LIN, Chen-Yi HUANG
  • Publication number: 20230022501
    Abstract: The present invention relates to a multistory electronic device testing apparatus, which mainly comprises a feeding and binning device, a multi-axis transfer device, a chip-testing device and a main controller. The feeding and binning device includes an upper module and a lower module. The chip-testing device includes a plurality of testing units arranged vertically. The main controller not only controls the feeding, binning and testing operations, but also controls the multi-axis transfer device to transfer an electronic device to be tested or a tested electronic device between the feeding and binning device and the chip-testing device. Accordingly, the three-dimensional arrangement of the feeding and binning module and the testing device is realized, and the accommodating capacity and the testing capacity for the electronic devices to be tested and the tested electronic devices can be increased.
    Type: Application
    Filed: June 7, 2022
    Publication date: January 26, 2023
    Inventors: Chin-Yi OUYANG, Chien-Ming CHEN, Wei-Cheng KUO, Xin-Yi WU, Iching TSAI
  • Publication number: 20230021896
    Abstract: A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.
    Type: Application
    Filed: July 26, 2021
    Publication date: January 26, 2023
    Inventors: Fu-Bang CHEN, Chih-Chiang CHANG, Chang-Ching HUANG, Chun-Ming LAI, Wen-Hsing HUANG, Tzeng-Guang TSAI, Kuo-Hsin HUANG
  • Publication number: 20230023295
    Abstract: The invention comprises a light emitting diode chip and a package substrate. The light emitting diode chip is provided with a semiconductor epitaxial structure, a lateral extending interface structure, a chip conductive structure, an N-type electrode located above the semiconductor epitaxial structure and a P-type bypass detection electrode located on the lateral extending interface structure. The chip conductive structure is provided with a P-type main electrode located on a lower side. The package substrate comprises a plurality of electrode contacts through which the N-type electrode, the P-type bypass detection electrode and the P-type main electrode are connected, and a process quality of a alternative substrate adhesive layer in one of the semiconductor epitaxial structure and the chip conductive structure and a chip-substrate bonding adhesive layer between the P-type main electrode and the package substrate is evaluated by detecting electrical characteristics.
    Type: Application
    Filed: July 26, 2021
    Publication date: January 26, 2023
    Inventors: Fu-Bang CHEN, Chih-Chiang CHANG, Chang-Ching HUANG, Chun-Ming LAI, Wen-Hsing HUANG, Tzeng-Guang TSAI, Kuo-Hsin HUANG
  • Publication number: 20230023705
    Abstract: A semiconductor device, includes: a first conductive type semiconductor region including a first semiconductor structure, wherein the first semiconductor structure includes one or more pairs of stack, the one or more pairs of stack respectively includes a first layer and a second layer, the first layer includes AlxGa1-xN, the second layer includes AlyGa1-yN, wherein 0?x<1, 0<y<1, x<y, wherein one of the one or more pairs of stack includes an interface region located between the first layer and the second layer adjacent to the first layer; a second conductive type semiconductor region located on the first conductive type semiconductor region; and an active region located between the first conductive type semiconductor region and the second conductive type semiconductor region; wherein the first semiconductor structure includes a first dopant having a first doping concentration with a peak value at the interface region.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 26, 2023
    Inventors: Chang-Hua HSIEH, Chia-Ming LIU, Chi-Hsiang YEH, Shuo-Wei CHEN, Yen-Kai YANG
  • Publication number: 20230024043
    Abstract: Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.
    Type: Application
    Filed: March 18, 2022
    Publication date: January 26, 2023
    Inventors: Po-Chen Lai, Ming-Chih Yew, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230023844
    Abstract: A position calibration system and method are disclosed, in which a control unit is provided to control a positioner sensing module to scan a circular positioner provided on a positioning substrate in a first direction and a second direction so as to acquire midpoints of two scanned line segments and acquire an intersection of lines extending from the two center points in a direction perpendicular to the first and the second directions as a calibration reference point, which correspond to a centroid (a center) of the circular positioner. The calibration reference point functions as a reference point for positioning the positioning substrate with respect to the positioner sensing module and is stored in a memory unit. The calibration reference point can be used as a positioning point during installation of a machine and can also be used for calibration of a position of the machine.
    Type: Application
    Filed: January 21, 2022
    Publication date: January 26, 2023
    Inventors: Chin-Yi Ouyang, Wei-Cheng Kuo, Chien-Ming Chen, Xin-Yi Wu
  • Publication number: 20230027287
    Abstract: Systems, and methods for automatically identifying an underground optical fiber cable length from DFOS systems in real time and pair it with GPS coordinates that advantageously eliminate the need for in-field inspection/work by service personnel to make such real-time distance/location determinations. As such, inefficient, error-prone and labor-intensive prior art methods are rendered obsolete. Operationally, our method disclosure involves driving vehicles including GPS to generate traffic patterns and automatically mapping traffic trajectory signals from a deployed buried fiber optic cable to locate geographic location(s) of the buried fiber optic cable. Traffic patterns are automatically recognized; slack in the fiber optic cable is accounted for; location of traffic lights and other traffic control devices/structures may be determined; and turns in the fiber optic cable may likewise be determined.
    Type: Application
    Filed: July 20, 2022
    Publication date: January 26, 2023
    Applicant: NEC LABORATORIES AMERICA, INC
    Inventors: Ming-Fang HUANG, Shaobo HAN, Yuheng CHEN, Milad SALEMI, Ting WANG
  • Patent number: 11564168
    Abstract: Apparatus and method for performing beam failure recovery in a wireless communication system are provided. The method performed by a User Equipment (UE) includes receiving, from a base station, a first bandwidth part (BWP) configuration corresponding to a first BWP, a second BWP configuration corresponding to a second BWP, and a BWP inactivity timer; determining whether a BFR procedure is triggered; when determining that the BFR procedure is triggered: stopping the BWP inactivity timer and performing BWP switching from the first BWP to the second BWP.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: January 24, 2023
    Assignee: FG Innovation Company Limited
    Inventors: Yu-Hsin Cheng, Hung-Chen Chen, Chie-Ming Chou
  • Patent number: 11560879
    Abstract: A solar-aided coal-fired flexible power generation system and an operating method thereof are provided. The system includes a coal-fired thermal power generation system and a high-temperature heat storage system coupled with solar thermal power generation; wherein a heat storage medium heater is arranged in the boiler flue; the flow rates of heat storage medium entering the solar heat collection device and the heat storage medium heater are adjusted by the regulating valve and the pump, eliminating irradiation fluctuation influences and maintaining stable power; a heat storage medium tank is used for peak shaving to reduce steam turbine output under stable boiler combustion; the flow and temperature of the feedwater entering the heat storage medium and feedwater heat exchanger are adjusted to realize rapid load cycling. The present invention can realize solar and coal-fired generation coupling, reduce coal consumption, and greatly improve the flexibility and economy.
    Type: Grant
    Filed: June 22, 2019
    Date of Patent: January 24, 2023
    Assignee: XI'AN JIAOTONG UNIVERSITY
    Inventors: Hui Yan, Ming Liu, Daotong Chong, Jinshi Wang, Weixiong Chen, Junjie Yan
  • Patent number: 11563088
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 24, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11562646
    Abstract: An advance in the art is made according to aspects of the present disclosure directed to distributed fiber optic sensing systems (DFOS), methods, and structures that advantageously monitor and identify—in real-time—roadway traffic and patterns across a multiple-lane highway by employing a multiple-transverse fiber optic cable arrangement of optical fiber cable positioned under the highway/roadway to detect, monitor, and/or identify traffic.
    Type: Grant
    Filed: April 4, 2021
    Date of Patent: January 24, 2023
    Inventors: Yuheng Chen, Ming-Fang Huang, Ting Wang, Jingnan Zhao
  • Patent number: 11563990
    Abstract: A media player system is provided for receiving and processing a media program that uses a time interval interval tD required to decode ND frames of the media program segment. The media system receives the requested media program segment, processes the segment and determines if the throughput of the media program differs from the desired presentation throughput by a tolerance amount. Both decoding and rendering performance are determined and used to determine presentation throughput, and to determine if heavier or lighter variants of the media program should be requested for subsequent media program segments.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: January 24, 2023
    Assignee: ARRIS Enterprises LLC
    Inventors: William S. Watson, Kuang Ming Chen, Nick Baciu
  • Publication number: 20230012682
    Abstract: Embodiments of this application disclose a virtual machine migration method. One example method includes: indicating, by a controller, a proxy virtual machine to mount a volume; replacing, by using the proxy virtual machine, a driver of an original platform in the volume with a driver of a target platform; and then, mounting a replaced volume to a target virtual machine.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 19, 2023
    Inventors: Ming LI, Leiqiang ZHANG, Si SHEN, Jishi LIANG, Tangzhen LI, Wenguang CHEN
  • Publication number: 20230018214
    Abstract: The invention provides a semiconductor bonding structure, the semiconductor bonding structure includes a first chip and a second chip which are bonded with each other, the first chip has a first bonding pad and the second bonding pad contacted and electrically connected to each other on a bonding interface, the first bonding pad and the second bonding pad are made of copper, and a heterogeneous contact combination in the first chip, the heterogeneous contact combination comprises a contact stack structure of a copper element, a tungsten element and an aluminum element, the tungsten element is located between the copper element and the aluminum element
    Type: Application
    Filed: August 10, 2021
    Publication date: January 19, 2023
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Lin Lu, Shou-Zen Chang, Ying-Tsung Chu, Chi-Ming Chen