Patents by Inventor Ming Chen

Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240373690
    Abstract: A display panel includes a display area (AA), an OLED, and a pixel drive circuit. The display panel includes: a base substrate, first and second power lines, and a common electrode layer. The first and second power lines are located in the display area, the orthographic projection of the first power line is extended along the first direction, and the orthographic projection of the second power line is extended along the second direction, and the second direction is intersected with the first direction, at least a part of the second power line is connected to at least a part of the first power line through a via hole. The common electrode layer is located on one side of the base substrate, the common electrode layer is used to form the second electrode of the OLED, and the common electrode layer is connected to the first and second power lines.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 7, 2024
    Inventors: Tiaomei ZHANG, Juntao CHEN, Ziyang YU, Zhiliang JIANG, Ming HU
  • Publication number: 20240373136
    Abstract: This document describes methods and systems for a hybrid white balance, HWB, mode (114), which is a hybrid of automatic and manual WB modes, in a camera system (104) of an electronic device (102). The HWB mode may provide options for a user to select a WB setting, via a camera user interface (118) in a live-preview mode (110), along a continuous WB-adjustment range. In this way, the user's desired color can be applied with respect to images or video captured by the camera system. The camera UI includes a manual WB control (112) to manually adjust the white balance. A WB module (108) determines target WB gains corresponding to the manual WB control relative to an initial automatic WB decision for a current frame displayed in the live-preview mode of the camera application. In aspects, a look-up-table correlating to the manual WB control is used to compute the target WB gains.
    Type: Application
    Filed: May 20, 2021
    Publication date: November 7, 2024
    Inventors: Liang Liang, Michelle Y. Chen, Isaac William Reynolds, Shih-Ming Wang
  • Publication number: 20240368401
    Abstract: Toughened polyamide composition including: (a) at least one polyamide; (b) at least one toughener component; and (c) at least one siloxane-based component having a viscosity of 1 mm2/s-100,000 mm2/s providing toughened polyamide composition with good impact strength; process for producing the toughened polyamide composition; and articles made from the toughened polyamide composition.
    Type: Application
    Filed: November 15, 2021
    Publication date: November 7, 2024
    Inventors: Tao Wang, Hongyu Chen, Xilun Weng, Kainan Zhang, Ming Ming, Wenke Miao, Wuye Ouyang, Andong Liu
  • Publication number: 20240372459
    Abstract: A driving device includes a first current source, a second current source, a first common-mode current elimination (CMCE) circuit, a second common-mode current elimination (CMCE) circuit, a current-to-voltage converter, and a first comparator. The current sources provide constant currents. The current-to-voltage converter includes a first current mirror and a second current mirror. The control terminal of the first current mirror is coupled to the second CMCE circuit. The control terminal of the second current mirror is coupled to the first CMCE circuit. The first current mirror and the second current mirror receive the constant currents, common-mode currents, and differential currents, thereby controlling the first CMCE circuit and the second CMCE circuit to generate a voltage difference that excludes a common-mode voltage corresponding to the common-mode currents. The first comparator receives the voltage difference to drive a field-effect transistor.
    Type: Application
    Filed: November 9, 2023
    Publication date: November 7, 2024
    Inventors: KE-HORNG CHEN, KUO-LIN ZHENG, YU-CHOU KO, KE-MING SU, YING-FENG WU
  • Publication number: 20240373642
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Yen-Chieh Huang, Po-Ting Lin, Song-Fu Liao, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240370379
    Abstract: An electronic device includes a memory usage identification circuit and a system-level cache (SLC). The memory usage identification circuit obtains a memory usage indicator that depends on memory usage of a storage space allocated in a system memory at which memory access is requested by a physical address. The SLC includes a cache memory and a cache controller. The cache controller performs cache management upon the cache memory according to the physical address and the memory usage indicator.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 7, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chun-Ming Su, Chih-Wei Hung, Yi-Lun Lin, Kun-Lung Chen, Po-Han Wang, Ming-Hung Hsieh, Yun-Ching Li
  • Publication number: 20240372759
    Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
  • Publication number: 20240372413
    Abstract: A wireless management system includes a controller and energy storage units. Each of the energy storage units includes an energy storage device and a node substrate. The wireless management system is configured to select a first node substrate from the node substrates based on a signal strength of each of first request signals to join a local network by the controller. The wireless management system is further configured to select a second node substrate from the node substrates based on the signal strength of each of second request signals to join the local network by the first node substrate. The wireless management system is further configured to assign a serial number corresponds to each of the energy storage units based on the local network by the controller.
    Type: Application
    Filed: October 24, 2023
    Publication date: November 7, 2024
    Inventors: Yu-Wei LEE, Chih-Kuan YEN, Chin-Ming CHEN
  • Publication number: 20240370631
    Abstract: A system including computer readable storage media including executable instructions and one or more processors configured to execute the executable instructions to obtain a schematic netlist and a performance specification for an integrated circuit, determine electrical constraints for nets in the schematic netlist based on the performance specification, determine physical constraints from the electrical constraints, rout the nets in the schematic netlist based on the electrical constraints and the physical constraints, and provide a data file of a layout.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Hsien Yu Tseng, Guan-Ruei Lu, Wei-Ming Chen, Chih.Chi. Hsiao
  • Publication number: 20240371881
    Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.
    Type: Application
    Filed: July 10, 2024
    Publication date: November 7, 2024
    Inventors: Kuan-Jung CHEN, Tsung-Lin LEE, Chung-Ming LIN, Wen-Chih CHIANG, Cheng-Hung WANG
  • Publication number: 20240371980
    Abstract: A method for making a semiconductor device includes: forming a first gate stack over a first fin; forming a first gate spacer extending along a side of the first gate stack; forming a second gate spacer over the first gate spacer; forming a third gate spacer over the second gate spacer, the third gate spacer; forming a source/drain region adjacent the third gate spacer; depositing an interlayer dielectric (ILD) over the source/drain region, the ILD including a third dielectric material; and removing at least a portion of the second gate spacer to form a void, while exposing a top surface of the ILD. The void includes a vertical portion extending between the first gate spacer and the source/drain region, and between the first gate spacer and the ILD. The void includes a horizontal portion extending beneath the source/drain region.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu Ming Hsiao, Ming-Jhe Sie, Hsiu-Hao Tsao, Hong Pin Lin, Che-fu Chen, An Chyi Wei, Yi-Jen Chen
  • Publication number: 20240369596
    Abstract: A supporting device and a protective case for a probe card are provided. The protective case includes the supporting device, a case body, an upper cover, and plural switching members. The supporting device has plural quick-release members and plural bevel grooves. The case body has plural arrangement grooves each configured to mate with the corresponding quick-release member to fasten the supporting device to the case body. The probe card is connected with a protecting cover that includes plural fastening members fastened to the probe card. When the protecting cover and the probe card connected therewith are placed on the supporting device, the bevel grooves actuate the fastening members and thereby unfasten the fastening members from the probe card. The switching members are provided on the case body and are each lockable to a corresponding engaging member on the upper cover to lock the upper cover the case body together.
    Type: Application
    Filed: November 27, 2023
    Publication date: November 7, 2024
    Inventors: MING-CHIEN CHIU, YUNG-CHIN PAN, YU-CHEN CHU, CHI-CHUAN HUANG
  • Publication number: 20240369599
    Abstract: A probe card device comprises a testing circuit board, at least one probe and an image capture module. The testing circuit board has a first surface and a second surface in opposite. The at least one probe is disposed on the first surface of the testing circuit board and electrically connected to the testing circuit board. The at least one probe has a probe head and the probe head has a first height to the first surface. The image capture module is disposed on the first surface of the testing circuit board, and is located adjacent to the probe. The image capture module has a head portion and the head portion has a second height to the first surface. Wherein, the second height is smaller than the first height, and the image capture module is aligned to the probe head to capture a visible light image from the probe head.
    Type: Application
    Filed: April 30, 2024
    Publication date: November 7, 2024
    Applicant: Silicon Future Manufacturing Company Ltd.
    Inventors: TIEN-CHIA LEE, HENG-RUI CHANG, YOU-CHEN LIN, MING-CHANG LIAO, WEN-TSUNG SUNG
  • Publication number: 20240371810
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Application
    Filed: July 14, 2024
    Publication date: November 7, 2024
    Inventors: Hsin-Chi CHEN, Hsun-Ying HUANG, Chih-Ming LEE, Shang-Yen WU, Chih-An YANG, Hung-Wei HO, Chao-Ching CHANG, Tsung-Wei HUANG
  • Publication number: 20240371829
    Abstract: A method of forming a semiconductor device package is provided. The method includes bonding a first package component and a second package component to a substrate, wherein the first and second package components are different types of electronic components that provide different functions; attaching at least one dummy die to the substrate, wherein the dummy die is electrically isolated from the substrate, wherein the first and second package components are disposed on two opposite sides of the dummy die; and disposing an underfill element between the substrate, the first package component, the second package component, and the dummy die, wherein the underfill element extends up along the sidewalls of the dummy die and laterally surrounds the sidewalls of the dummy die in a top view, wherein the underfill element has a maximum height lower than the top surface of the dummy die.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Che-Chia YANG, Shu-Shen YEH, Po-Chen LAI, Ming-Chih YEW, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20240370716
    Abstract: Methods and apparatus for discrimitive semantic transfer and physics-inspired optimization in deep learning are disclosed. A computation training method for a convolutional neural network (CNN) includes receiving a sequence of training images in the CNN of a first stage to describe objects of a cluttered scene as a semantic segmentation mask. The semantic segmentation mask is received in a semantic segmentation network of a second stage to produce semantic features. Using weights from the first stage as feature extractors and weights from the second stage as classifiers, edges of the cluttered scene are identified using the semantic features.
    Type: Application
    Filed: July 11, 2024
    Publication date: November 7, 2024
    Inventors: Anbang YAO, Hao ZHAO, Ming LU, Yiwen GUO, Yurong CHEN
  • Publication number: 20240371867
    Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Yi-Chen HO, Chien LIN, Tzu-Wei LIN, Ju Ru HSIEH, Ching-Lun LAI, Ming-Kai LO
  • Publication number: 20240371670
    Abstract: A protection device for a substrate container includes a container door and a limiter for pushing against and securing a substrate, a support member and an elastic connecting component for engaging and securing the container body, and an antistatic member having elasticity interference to provide an electrostatic dissipation path as electrostatic protection for the substrate. The protection device for a substrate container improves a protection effect of a substrate stored in the substrate container, and prevents hazards to a substrate caused by vibration, dust, and static electricity.
    Type: Application
    Filed: November 29, 2023
    Publication date: November 7, 2024
    Inventors: MING-CHIEN CHIU, YUNG-CHIN PAN, YU-CHEN CHU, CHI-CHUAN HUANG, CHENG-EN CHUNG
  • Publication number: 20240371666
    Abstract: Some implementations herein provide for a system and methods for in-line monitoring of a sealant being dispensed by a jet nozzle in a beveled region along a perimeter of a stack of semiconductor substrates. The system includes an automated optical inspection system. During the dispensing of the sealant by the jet nozzle, the automated optical inspection system may monitor an amount of an accumulation of the sealant within the beveled region.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 7, 2024
    Inventors: Hau-Yi HSIAO, Kuo-Ming WU, Sheng-Chau CHEN, Ru-Liang LEE
  • Publication number: 20240371960
    Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor device includes a first gate structure engaging a plurality of first channel members that are vertically stacked, a first source/drain feature abutting the first channel members, a second gate structure engaging a plurality of second channel members that are vertically stacked, a second source/drain feature abutting the second channel members, a first backside dielectric feature disposed directly under the first gate structure, and a second backside dielectric feature disposed directly under the second gate structure. A number of the first channel members is larger than a number of the second channel members. A top surface of the first backside dielectric feature is below a top surface of the second backside dielectric feature.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Kuo-Cheng Chiang, Yen-Ming Chen, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng