Patents by Inventor Ming Chen

Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10855162
    Abstract: The present invention provides a secondary side of a linear motor, which mainly includes a base, a combining mechanism and multiple magnetic members, wherein the base has multiple plates that are sequentially stacked into a block; the combining mechanism is configured to combine the plate-shaped bodies; and the magnetic members are disposed on the base in a separated manner.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 1, 2020
    Assignee: HIWIN MIKROSYSTEM CORP.
    Inventors: Cheng-Te Chi, Chao-Chin Teng, Hui-Ming Chen
  • Patent number: 10854550
    Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: December 1, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sheng-Ming Wang, Tien-Szu Chen, Wen-Chih Shen, Hsing-Wen Lee, Hsiang-Ming Feng
  • Patent number: 10854605
    Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li Chiang, Cheng-Yi Peng, Tsung-Yao Wen, Yee-Chia Yeo, Yen-Ming Chen
  • Patent number: 10854729
    Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
  • Patent number: 10854726
    Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200374776
    Abstract: A user equipment (UE) comprises a processor configured to execute executable instructions to receive configuration information associated with at least two uplink carriers from a base station, the at least two uplink carriers including a supplementary uplink carrier and a normal uplink carrier, select one of the at least two uplink carriers of the base station if a power of a first downlink reference signal from the base station and measured by the UE is below a first threshold value, select a contention-free random access (CFRA) resource associated with a second downlink reference signal on the selected uplink carrier of the base station if a power of the second downlink reference signal from the base station and measured by the UE is above a second threshold value, and perform a random access procedure with the base station by using the selected CFRA resource over the selected uplink carrier.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 26, 2020
    Inventors: MEI-JU SHIH, CHIE-MING CHOU, HUNG-CHEN CHEN, CHIA-HUNG WEI, YUNG-LAN TSENG, YU-HSIN CHENG
  • Publication number: 20200371425
    Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Chun-Chieh TIEN, Cheng-Hsuen CHIANG, Chih-Ming CHEN, Cheng-Ming LIN, Yen-Wei HUANG, Hao-Ming CHANG, Kuo-Chin LIN, Kuan-Shien LEE
  • Publication number: 20200373345
    Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: CHIH-CHANG HUANG, CHI-MING LU, JIAN-MING CHEN, JUNG-CHIH TSAO, YAO-HSIANG LIANG
  • Publication number: 20200373239
    Abstract: A method includes depositing an etch stop layer over a non-insulator structure and a dielectric layer over the etch stop layer; etching the dielectric layer to form a first hole in the dielectric layer; deepening the first hole into the etch stop layer such that the non-insulator structure is exposed at a bottom of the deepened hole; after the non-insulator structure is exposed, performing a cleaning operation to remove etch byproducts from the deepened first hole, wherein the cleaning operation results in lateral recesses laterally extending from a bottom portion of the deepened first hole into the etch stop layer; depositing a first diffusion barrier layer into the deepened first hole until the lateral recesses are overfilled; depositing a second diffusion barrier layer over the first diffusion barrier layer; and depositing one or more conductive layers over the second diffusion barrier layer.
    Type: Application
    Filed: August 8, 2020
    Publication date: November 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chen CHAN, Shin-Yi YANG, Ming-Han LEE
  • Publication number: 20200369511
    Abstract: The present disclosure relates to a microphone. In some embodiments, the microphone may comprise a diaphragm, a backplate, and a sidewall stopper. The diaphragm has a venting hole disposed therethrough. The backplate is disposed over and spaced apart from the diaphragm. The sidewall stopper is disposed along a sidewall of the diaphragm exposing to the venting hole. Thus, the sidewall stopper is not limited by a distance between the movable part and the stable part of the microphone. Also, the sidewall stopper does not alternate the shape of movable part, and thus will less likely introduce crack to the movable part. In some embodiments, the sidewall stopper may be formed like a sidewall stopper by a self-alignment process, such that no extra mask is needed.
    Type: Application
    Filed: August 11, 2020
    Publication date: November 26, 2020
    Inventors: Shih-Wei Lin, Chang-Ming Wu, Ting-Jung Chen
  • Publication number: 20200373405
    Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a first gate spacer, and an epitaxy structure. The substrate has a semiconductor fin. The isolation structure is over the substrate and laterally surrounds the semiconductor fin. The first gate structure is over the substrate and crosses the semiconductor fin. The first gate spacer extends along a sidewall of the first gate structure, in which the first gate spacer has a stepped sidewall distal to the first gate structure. The epitaxy structure is over the semiconductor fin, in which the epitaxy structure is in contact with the stepped sidewall of the first gate spacer.
    Type: Application
    Filed: August 8, 2020
    Publication date: November 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lun CHEN, Bau-Ming WANG, Chun-Hsiung LIN
  • Publication number: 20200374342
    Abstract: A method for scalable and secure vehicle to everything communications may include receiving telematics data from a plurality of vehicles and tracking the vehicles within a window which is centered based on the telematics data. The position of the window may be determined based on positions of the vehicles. The method may include dividing the vehicles within the window into partitions having sizes based on a maximum number of vehicles within the partitions, and determining a metric representing a suitability of communications between the vehicles in the window.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Inventors: Ming Chen, Pramod Kalyanasundaram, Jianxiu Hao, Dahai Ren
  • Publication number: 20200373267
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20200370837
    Abstract: A complex vapor chamber structure includes a main body and at least one tubular body. The main body has a first chamber, a first opening and a second opening. A first capillary structure is disposed in the first chamber. A working fluid is filled in the first chamber. The first and second openings pass through one face of the main body to communicate with the first chamber. The tubular body has a first end, a second end and a passage. The first and second ends are respectively correspondingly inserted in the first and second openings, whereby the passage of the tubular body communicates with the first chamber via the first and second ends to form a loop for vapor-liquid circulation.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Inventors: Xue-Hui Liu, Jiu-Ming Chen, Jian-Wu Yin
  • Publication number: 20200371056
    Abstract: A gas sensing device comprises a silicon substrate, an insulating layer, a plasma treatment layer, a metal electrode and a sensing layer. The insulating layer is formed on the silicon substrate. The plasma treatment layer is formed on the insulating layer. The metal electrode is formed on the portion of the plasma treatment layer. The sensing layer is formed on a surface of the metal electrode and the plasma treatment layer. Through plasma treatment for the substrate and printing graphene film on the substrate and the electrode, the adsorption characteristics of gas selection ratio for graphene is improved, and the processing time of the plasma treatment is adjusted to optimize the sensing characteristics.
    Type: Application
    Filed: September 9, 2019
    Publication date: November 26, 2020
    Inventors: CHAO-SUNG LAI, CHIA-MING YANG, TSUNG-CHENG CHEN, YU-CHENG YANG
  • Publication number: 20200374782
    Abstract: A method of wireless communications performed by a user equipment (UE) is provided. The method includes performing an on-demand system information (SI) request procedure in a cell; and performing an error handling procedure if the on-demand SI request procedure in the cell is unsuccessful. The error handling procedure includes storing SI request failure information.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Inventors: HUNG-CHEN CHEN, CHIE-MING CHOU, YUNG-LAN TSENG
  • Publication number: 20200369512
    Abstract: The present disclosure relates to a method of manufacturing a MEMS device. In some embodiments, a first interlayer dielectric layer is formed over a substrate, and a diaphragm is formed over the first interlayer dielectric layer. Then, a second interlayer dielectric layer is formed over the diaphragm. A first etch is performed to form an opening through the second interlayer dielectric layer and the diaphragm and reaching into an upper portion of the first interlayer dielectric layer. A second etch is performed to the first interlayer dielectric layer and the second interlayer dielectric layer to form recesses above and below the diaphragm and to respectively expose a portion of a top surface and a portion of a bottom surface of the diaphragm. A sidewall stopper is formed along a sidewall of the diaphragm into the recesses of the first interlayer dielectric layer and the second interlayer dielectric layer.
    Type: Application
    Filed: August 11, 2020
    Publication date: November 26, 2020
    Inventors: Shih-Wei Lin, Chang-Ming Wu, Ting-Jung Chen
  • Patent number: 10848084
    Abstract: An electrical switch unit for use with an electrical device to control operation of a DC motor of the electrical device, the electrical switch unit comprising: a housing which houses a pair of electrical switching contacts, and, an actuator operably connected with at least one of the pair of electrical switching contacts, the actuator being configured for movement relative to the pair of electrical switching contacts so as to arrange the pair of electrical switching contacts into at least one of a closed configuration wherein power is able to be supplied from the DC power source to the DC motor via the pair of electrical switching contacts, and, an opened configuration wherein power is not able to be supplied from the DC power source to the DC motor via the pair of electrical switching contacts; a signaling module associated with the electrical switch unit comprising signaling circuitry for sensing the movement of the actuator and outputting a signaling module signal indicative of the sensed movement or posit
    Type: Grant
    Filed: August 11, 2018
    Date of Patent: November 24, 2020
    Assignees: Defond Electech Co., Ltd., Defond Components Limited
    Inventors: Cheng Chen Nieh, Wai Man Wong, Ming Leong Kong, Pat On Kwok
  • Patent number: 10843571
    Abstract: The present disclosure relates to a novel high-performance repairable sliding plate of a pantograph of an electric locomotive and a manufacturing method thereof. The sliding plate includes a monometallic substrate and a conductive, wear-resistant, anticorrosion and self-lubricating coating integrated with the substrate. The coating is formed by plasma spraying Cu—TiO2 core-shell composite powder on the monometallic substrate directly, and includes the following components by mass percent: 60-70% of Ti4O7, 15-25% of Cu, 10-15% of TixO(2x?1) and 5-10% of TiO2, where 5?x?10. The multifunctional composite coating is the working layer of the sliding plate of the present disclosure, and the damage of the coating can be repaired by plasma spraying with the composite powder, thereby recovering dimensional accuracy and service performance.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: November 24, 2020
    Assignee: ARMY ACADEMY OF ARMORED FORCES
    Inventors: Guozheng Ma, Haidou Wang, Yiwen Wang, Pengfei He, Shuying Chen, Ming Liu, Zhiguo Xing, Haijun Wang, Binshi Xu
  • Patent number: 10845008
    Abstract: An LED filament comprises at least one LED section, a conductive section, two conductive electrodes and a light conversion layer. The conductive section is used to electrically connect two adjacent LED sections. The two conductive electrodes are electrically connected to each of the LED sections. Each of the LED sections includes at least two LED chips electrically connected to each other. The light conversion layer covers the LED sections, the conductive sections and the conductive electrodes, and a part of the two electrodes is exposed respectively. Since the LED filament includes the LED section and the conductive section, when the LED filament is bent, the stress is easily concentrated on the conductive section. Therefore, the breakage probability of the conductive wires connected within the LED section is reduced during bending. The quality of the LED filament and its application is improved.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 24, 2020
    Assignee: ZHEJIANG SUPER LIGHTING ELECTRIC APPLIANCE CO., LTD.
    Inventors: Tao Jiang, Wei-Hong Xu, Yukihiro Saito, Hayato Unagiike, Ai-Ming Xiong, Jun-Feng Xu, Yi-Ching Chen