Abstract: The application discloses a color filter substrate, a display panel and a display device. The color filter substrate includes a base substrate, a light-shielding portion and a plurality of light-filtering portions. The plurality of light-shielding portions are arranged on the base substrate at intervals, the light-filtering portion is arranged between the plurality of light-shielding portions, the light-filtering portion includes a first light-filtering portion and at least two second light-filtering portions, the first light-filtering portion is arranged between the two second light-filtering portions, the first light-filtering portion includes a color resist material and a high-refractive material, and the at least two second light-filtering portions includes a transparent material.

Abstract: A method of forming a semiconductor device includes following steps. A first organic layer is formed to cover a first conductive layer. A first opening is formed in the first organic layer to expose a first surface of the first conductive layer. A first silicon layer is formed on a sidewall of the first opening and the first surface of the first conductive layer. A first dielectric layer is formed on the sidewall of the first opening and the first surface of the first conductive layer over the first silicon layer. By using a first mask, portions of the first silicon layer and the first dielectric layer on the first surface are simultaneously removed to expose the first surface, wherein after removing the portions of the first silicon layer and the first dielectric layer, the first dielectric layer covers a top surface of the first silicon layer.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.

Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of finFETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a first substrate, forming at least one circuit element at least partially from a semiconductor material of a second substrate, bonding the first substrate to the second substrate, etching a through via extending through the second substrate to partially expose the conductive layer, depositing at least one conductive material in the through via to form a conductive through via electrically coupled to the conductive layer and over the second substrate to form a first contact structure electrically coupling the conductive through via to the at least one circuit element. The at least one circuit element includes at least one of a Schottky diode, a capacitor, or a resistor.

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.

Abstract: A method for correcting translation errors when performing GUI globalization testing is disclosed. In one embodiment, such a method takes a screenshot of a graphical user interface (GUI). The method further enables a user to select text in the screenshot. In certain embodiments, one or more of the text and coordinates associated with the text are stored in picture attributes associated with the screenshot. In response to the selection, the method automatically retrieves a file in which at least some portion of the text is contained. The method automatically locates, within the file, the portion, and enables the user to update the portion in the file in order to update corresponding text in the graphical user interface. In certain embodiments, the method provides a probability percentage associated with the file that indicates a probability that the text in the file links to the selected text in the graphical user interface.

Abstract: A semiconductor device including a magnetic random access memory (MRAM) cell includes first and second magnetic random access memory (MRAM) cell structures disposed over a substrate. Each of the first and second MRAM cell structures includes a bottom electrode, a magnetic tunnel junction (MTJ) stack, and a top electrode. The semiconductor device further includes a first insulating cover layer covering sidewalls of each of the first and second MRAM cell structures, and a second insulating cover layer disposed over the first insulating cover layer. The semiconductor device further includes a bottom dielectric layer filling a space between the first and second MRAM cell structures, and an upper dielectric layer disposed over the bottom dielectric layer. Each of the first insulating cover layer and the second insulating cover layer is discontinuous between the first MRAM cell structure and the second MRAM cell structure.

Abstract: The treatment system provides a feature that may reduce cost of the electrochemical plating process by reusing the virgin makeup solution in the spent electrochemical plating bath. The treatment system provides a rotating filter shaft which receives the spent electrochemical plating bath and captures the additives and by-products created by the additives during the electrochemical plating process. To capture the additives and the by-products, the rotating filter shaft includes one or more types of membranes. Materials such as semi-permeable membrane are used to capture the used additives and by-products in the spent electrochemical plating bath. The treatment system may be equipped with an electrochemical sensor to monitor a level of additives in the filtered electrochemical plating bath.

Abstract: An inertia flywheel assembly and a system thereof are disclosed. The system includes a driving device, an inertia flywheel assembly, a transmission member, a flywheel monitor unit, an abort unit and at least one output device. The inertia flywheel assembly comprises a first inertia flywheel and at least one second inertia flywheel, each inertia flywheel has a flywheel body and an axle, the axle is fixed to the axis of the flywheel body, and the flywheel body could spin via the axle. The flywheel body is a streamlined body. A first transmission portion is disposed on the circumference of the flywheel body of the first inertia flywheel. A second transmission portion is disposed on the axle of each second inertia flywheel. The second transmission portion is coupled to the first transmission portion. The output device is coupled to the axle of the second inertia flywheel.

Abstract: A semiconductor device includes in a transistor layer, components of corresponding transistors (transistor components); in corresponding layers below the transistor layer (sub-TR layers), various non-dummy structures (non-dummy sub-TR structures) coupled to the transistor components and which are included because the semiconductor device has a buried power rail (BPR) architecture; and in corresponding layers over the transistor layer (supra-TR layers), various dummy structures (dummy supra-TR structures) which are included as artifacts resulting from the semiconductor device being based on a dual-architecture-compatible design which is substantially equally suitable either to adaptation into a non-BPR architecture or adaptation into the BPR architecture; and the semiconductor device being an inductor.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a functional cell region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region including a first cutting feature and a first contact rail in the first cutting feature. The semiconductor structure also includes a first power rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell and including a second cutting feature and second contact rail in the second cutting feature. The semiconductor structure also includes an insulating strip extending from the first cutting feature to the second cutting feature in a first direction.

Abstract: An inverter-based comparator includes an output stage circuit including a P-type output transistor and an N-type output transistor; a first inverter having a first transition voltage with an input node coupled to an input voltage and an output node generating a first inverted voltage and coupled to a gate of the N-type output transistor; and a second inverter having a second transition voltage with an input node coupled to the input voltage and an output node generating a second inverted voltage and coupled to a gate of the P-type output transistor. The first inverter and the second inverter each includes an inverter that includes a first inverter branch composed of at least one first P-type transistor and at least one first N-type transistor; and a second inverter branch composed of at least one second P-type transistor, at least one second N-type transistor and at least two tuning switches.

Abstract: A display substrate includes a base, a plurality of light-emitting devices disposed on a side of the base, and a light adjustment layer. The plurality of light-emitting devices are spaced apart from each other. At least part of the light adjustment layer is located in gaps among the plurality of light-emitting devices, so that side walls of at least one of the plurality of light-emitting devices are surrounded by the light adjustment layer. A material of the light adjustment layer includes a light-absorbing material. The light adjustment layer is configured to absorb light incident on the light adjustment layer.

Abstract: In communication applications, aggregate source image data at a transmitter exceeds the data that is needed to display a rendering of a viewport at a receiver. Improved streaming techniques that include estimating a location of a viewport at a future time. According to such techniques, the viewport may represent a portion of an image from a multi-directional video to be displayed at the future time, and tile(s) of the image may be identified in which the viewport is estimated to be located. In these techniques, the image data of tile(s) in which the viewport is estimated to be located may be requested at a first service tier, and the other tile in which the viewport is not estimated to be located may be requested at a second service tier, lower than the first service tier.

Abstract: An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a reference circuit that generates a first reference with a first non-zero temperature coefficient and a second reference with a second temperature coefficient having a different magnitude than the first non-zero temperature coefficient. A detector circuit on the integrated circuit, having temperature and process variation compensation, converts a difference between the first and second references into a digital signal indicating temperature on the integrated circuit.

Abstract: A method for fabricating a semiconductor device is provided. The method includes coating a photoresist film over a target layer over a semiconductor substrate; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer along a direction tilted with respect to a normal direction of the semiconductor substrate, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.

Abstract: A semiconductor structure includes a first dielectric layer, an electrode in the first dielectric layer, a second dielectric layer in the electrode, and a phase change material over the first dielectric layer, the electrode, and the second dielectric layer. According to some embodiments, an uppermost surface of the electrode is at least one of above an uppermost surface of the first dielectric layer, above an uppermost surface of the second dielectric layer, or above a lowermost surface of the phase change material.