Abstract: A flow meter includes a meter body and a pressure sensor. The meter body has a liquid impact surface, a sensing surface opposite to the liquid impact surface, and a mounting hole extending from the sensing surface toward the liquid impact surface. The mounting hole is a blind hole. The pressure sensor is mounted in the mounting hole, and has a resistance value that can be measured and that can be changed correspondingly with a change in liquid pressure caused by a change in flow rate. A device for producing an active hydroxyl free radical solution is also disclosed.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

Abstract: A safety pin locking device for workpiece turnover includes a safety pin, a triangular lock plate, an elastic positioning pin, and a lockset. The safety pin is configured to be inserted into a base and an overturnable workpiece to lock an angle of the overturnable workpiece relative to the base. A first corner end of the triangular lock plate is connected to an axial surface of the safety pin by a fastener, and the triangular lock plate can rotate around the fastener. The elastic positioning pin is mounted at a second corner end of the triangular lock plate and is configured to be inserted into positioning counterbores at two different positions on the axial surface of the safety pin to limit a position of the triangular lock plate. The lockset is mounted at a third corner end of the triangular lock plate.

Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer and one or more first conductive features disposed in the first dielectric layer. The one or more first conductive features includes a first metal. The structure further includes a plurality of graphene layers disposed on each of the one or more first conductive features, the plurality of graphene layers include a second metal intercalated therebetween, and the second metal is different from the first metal.

Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.

Abstract: An optical module includes a housing and a release mechanism. The housing includes an outer lateral surface. The release mechanism includes an arm and a releasing component. The arm is disposed on the outer lateral surface and movable relative to the housing. The releasing component is disposed on the outer lateral surface and includes a pivot, a releasing portion and a pressed portion. The pivot is between the releasing portion and the pressed portion. The pivot is disposed on the housing. The arm pushes the pressed portion to pivot the releasing component. At an idle state of the release mechanism, a movement of the housing is restricted by an interference between a flexible counterpart of a cage and the housing. At a releasing state of the release mechanism, the releasing portion deforms the flexible counterpart, thereby removing the interference between the flexible counterpart and the housing.

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride and ammonia.

Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure having a dielectric structure and multiple wiring layers in or over the dielectric structure and a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure also includes a first chip structure bonded to the redistribution structure and electrically insulated from the shield bump structure, and the first chip structure has a first sidewall. The chip package structure further includes a second chip structure bonded to the redistribution structure and electrically insulated from the shield bump structure. The first chip structure and the second chip structure are spaced apart from each other by a gap, and the shield bump structure extends across the gap. The first sidewall faces away from the second chip structure, and the shield bump structure extends across the first sidewall.

Abstract: A semiconductor device includes a bottom wafer, a top wafer bonded to the bottom wafer, a first dielectric layer, a second dielectric layer, a deep via conductor structure, and a connection pad. The top wafer includes a first interconnection structure. The first dielectric layer is disposed on the top wafer. The second dielectric layer is disposed on the first dielectric layer. The deep via conductor structure penetrates through the second dielectric layer and the first dielectric layer and is connected with the first interconnection structure. The connection pad is disposed on the second dielectric layer and the deep via conductor structure. A first portion of the second dielectric layer is sandwiched between the connection pad and the first dielectric layer. A second portion of the second dielectric layer is connected with the first portion, and a thickness of the second portion is less than a thickness of the first portion.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Abstract: A coating system and a method for using such a system comprising a vessel, a flexible container within the vessel, and a coating apparatus. The flexible container includes an outlet port, wherein the flexible container is configured to contract in response to an increase in pressure within the vessel. The flexible container is configured to output a coating composition through the outlet port in response to contraction. The coating apparatus is configured to receive the coating composition from the outlet port and in some embodiments, deliver the coating composition to a wafer surface.

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

Abstract: A method includes forming a dielectric layer over a substrate; forming a patterned amorphous silicon layer over a dielectric layer; depositing a first spacer layer over the patterned amorphous silicon layer; depositing a second spacer layer over the first spacer layer; forming a photoresist having an opening over the substrate; depositing a hard mask layer in the opening of the photoresist; after depositing the hard mask layer in the opening of the photoresist, removing the photoresist; and performing an etching process to etch the dielectric layer by using the patterned amorphous silicon layer, the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask, in which the etching process etches the second spacer layer at a slower etch rate than etching the first spacer layer.

Abstract: A semiconductor structure includes a third metal layer immediately above a second metal layer that is over a first metal layer. The second metal layer includes magnetic tunneling junction (MTJ) devices in a memory region and a first conductive feature in a logic region. Each MTJ device includes a bottom electrode and an MTJ stack over the bottom electrode. The third metal layer includes a first via electrically connecting to the first conductive feature, and a slot via over and electrically connecting to the MTJ stack of the MTJ devices. The slot via occupies space extending continuously and laterally from a first one to a last one of the MTJ devices. The first via is as thin as or thinner than the slot via. The third metal layer further includes second and third conductive features electrically connecting to the first via and the slot via, respectively.

Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.

Abstract: Some implementations described herein provide techniques and apparatuses for determining a performance of a dry-clean operation within a deposition tool. A cleaning-control subsystem of the deposition tool may include a gas concentration sensor and a temperature sensor mounted in an exhaust system of the deposition tool to monitor the dry-clean operation. The gas concentration sensor may provide data related to a concentration of a chemical compound in a cleaning gas, where the chemical compound is a bi-product of the dry-clean operation. The temperature sensor may provide temperature data related to an exothermic reaction of the dry-clean operation. Such data may be used to determine an efficiency and/or an effectiveness of the dry-clean operation within the deposition tool.

Abstract: A handling device (100) for automatically exchanging component feeders (390) at a pick and place station (4000) for assembling component carriers with electronic components is described. The handling device (100) comprises (a) a chassis (110); (b) a drive (120) with a stationary drive component (122) attached to the chassis (110) and a movable drive component (126) which can be spatially positioned along a y-direction; (c) a first coupling device (130a) which is attached to the movable drive component (126) and which has a first coupling element (234) and a first actuator (232); (d) a second coupling device (130b), which is also attached to the movable drive component (126) and which comprises a second coupling element (234) and a second actuator (232); and (e) a control device (102), which is configured to individually actuate the first actuator (232) and to individually actuate the second actuator (232).

Abstract: A method of forming a semiconductor device includes following steps. A sacrificial layer is formed in an opening of a substrate. A first doped region is formed in the opening over the sacrificial layer. The substrate is flipped. A portion of the substrate is removed to expose the sacrificial layer. The sacrificial layer is replaced with a first contact.