Abstract: A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of the gate electrode along a base of the gate electrode. Optionally, an underlying dielectric layer, such as a shallow trench isolation, may be recessed under the notch, thereby reducing gap fill issues.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes the following operations: providing a vertical structure over a substrate; forming a first dielectric layer over the vertical structure and the substrate; laterally etching a sidewall of the first dielectric layer; replacing a portion of the first dielectric layer over the vertical structure with a second dielectric layer; and etching a portion of the first dielectric layer to expose the lateral surface of the vertical structure.

Abstract: A method of forming a FinFET is provided. A gate oxide layer and a dummy poly layer are substantially simultaneously etched using an etchant having a higher selectivity on the gate oxide layer than on the dummy poly layer. The gate oxide layer and the dummy poly layer are intersected with the gate oxide layer over a fin layer of the FinFET.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including a gate dielectric and a gate disposed over the gate dielectric, and reshaping a top surface of the gate to form a gate with a rounded profile.

Abstract: A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of the gate electrode along a base of the gate electrode. Optionally, an underlying dielectric layer, such as a shallow trench isolation, may be recessed under the notch, thereby reducing gap fill issues.

Abstract: A structure includes a substrate, a gate structure over the substrate, a dielectric layer over the substrate, and a cap over a gate electrode of the gate structure. Top surfaces of the dielectric layer and gate electrode are co-planar. The gate structure extends a gate lateral distance between first and second gate structure sidewalls. The cap extends between first and second cap sidewalls. A first cap portion extends from a midline of the gate structure laterally towards the first gate structure sidewall and to the first cap sidewall a first cap lateral distance, and a second cap portion extends from the midline laterally towards the second gate structure sidewall and to the second cap sidewall a second cap lateral distance. The first cap lateral distance and the second cap lateral distance are at least half of the gate lateral distance.

Abstract: An apparatus and method, as may be used for predicting solar irradiance variation, are provided. The apparatus may include a solar irradiance predictor processor (10) configured to process a sequence of images (e.g., sky images). The irradiance predictor processor may include a cloud classifier module (18) configured to classify respective pixels of an image of a cloud to indicate a solar irradiance-passing characteristic of at least a portion of the cloud. A cloud motion predictor (22) may be configured to predict motion of the cloud over a time horizon. An event predictor (24) may be configured to predict over the time horizon occurrence of a solar obscuration event. The prediction of the solar obscuration event may be based on the predicted motion of the cloud. The event predictor may include an irradiance variation prediction for the obscuration event based on the solar irradiance-passing characteristic of the cloud.

Abstract: The disclosure relates to a dummy gate electrode of a semiconductor device. An embodiment comprises a substrate comprising a first surface; an insulation region covering a portion of the first surface, wherein the top of the insulation region defines a second surface; and a dummy gate electrode over the second surface, wherein the dummy gate electrode comprises a bottom and a base broader than the bottom, wherein a ratio of a width of the bottom to a width of the base is from about 0.5 to about 0.9.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

Abstract: A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of the gate electrode along a base of the gate electrode. Optionally, an underlying dielectric layer, such as a shallow trench isolation, may be recessed under the notch, thereby reducing gap fill issues.

Abstract: The disclosure relates to a dummy gate electrode of a semiconductor device. An embodiment comprises a substrate comprising a first surface; an insulation region covering a portion of the first surface, wherein the top of the insulation region defines a second surface; and a dummy gate electrode over the second surface, wherein the dummy gate electrode comprises a bottom and a base broader than the bottom, wherein a ratio of a width of the bottom to a width of the base is from about 0.5 to about 0.9.

Abstract: Homography-based imaging apparatus and method are provided. The apparatus may include a processor (44) coupled to process respective sequences of sky images respectively acquired by physical image acquisition devices 181 and 182 at respective spaced apart locations (e.g., P1, P2). The processor may include an image alignment module (32) configured to spatially relate respective views of at least one object (e.g., clouds, aerial vehicles) visible in the respective sequences of the sky images based on homography (42) of at least one astronomical image acquired at each spaced apart location. The astronomical image may include a number of spatial references corresponding to respective astronomical body positions located practically at infinity relative to a respective distance between the spaced apart locations. Further views (synthetic views) may be generated at selectable new locations (e.g., P3, P4, P5, P6), without actually having any physical image acquisition devices at such selectable locations.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

Abstract: The disclosure relates to a dummy gate electrode of a semiconductor device. An embodiment comprises a substrate comprising a first surface; an insulation region covering a portion of the first surface, wherein the top of the insulation region defines a second surface; and a dummy gate electrode over the second surface, wherein the dummy gate electrode comprises a bottom and a base broader than the bottom, wherein a ratio of a width of the bottom to a width of the base is from about 0.5 to about 0.9.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

Abstract: A method includes providing a first mask pattern over a substrate, forming first spacers adjoining sidewalls of the first mask pattern, removing the first mask pattern, forming second spacers adjoining sidewalls of the first spacers, forming a filling layer over the substrate and between the second spacers, and forming a second mask pattern over the substrate.

Abstract: Homography-based imaging apparatus and method are provided. The apparatus may include a processor (44) coupled to process respective sequences of sky images respectively acquired by physical image acquisition devices 181 and 182 at respective spaced apart locations (e.g., P1, P2). The processor may include an image alignment module (32) configured to spatially relate respective views of at least one object (e.g., clouds, aerial vehicles) visible in the respective sequences of the sky images based on homography (42) of at least one astronomical image acquired at each spaced apart location. The astronomical image may include a number of spatial references corresponding to respective astronomical body positions located practically at infinity relative to a respective distance between the spaced apart locations. Further views (synthetic views) may be generated at selectable new locations (e.g., P3, P4, P5, P6), without actually having any physical image acquisition devices at such selectable locations.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a semiconductor substrate and forming a gate trench therein. The method also includes filling in the gate trench partially with a work-function (WF) metal stack, and filling in the remaining gate trench with a dummy-filling-material (DFM) over the WF metal stack. A sub-gate trench is formed by etching-back the WF metal stack in the gate trench, and is filled with an insulator cap to form an isolation region in the gate trench. The DFM is fully removed to from a MG-center trench (MGCT) in the gate trench, which is filled with a fill metal.

Abstract: An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresistlayer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresistlayer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant.