Patents by Inventor Ming-Ching Chang

Ming-Ching Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130187235
    Abstract: The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Sheng Huang, Tzu-Yen Hsieh, Ming-Ching Chang, Chao-Cheng Chen, Chia-Jen Chen
  • Patent number: 8489218
    Abstract: The present disclosure provides a method of chamber match. The method includes identifying a golden chamber designed operable to implement a semiconductor process; identifying a reference chamber designed operable for the semiconductor process; and extracting a matching index of a processing chamber relative to the golden chamber and the reference chamber using a dynamic variable analysis.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: July 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bing-Hung Chen, Ming-Ching Chang
  • Publication number: 20130152997
    Abstract: An apparatus and method, as may be used for predicting solar irradiance variation, are provided. The apparatus may include a solar irradiance predictor processor (10) configured to process a sequence of images (e.g., sky images). The irradiance predictor processor may include a cloud classifier module (18) configured to classify respective pixels of an image of a cloud to indicate a solar irradiance-passing characteristic of at least a portion of the cloud. A cloud motion predictor (22) may be configured to predict motion of the cloud over a time horizon. An event predictor (24) may be configured to predict over the time horizon occurrence of a solar obscuration event. The prediction of the solar obscuration event may be based on the predicted motion of the cloud. The event predictor may include an irradiance variation prediction for the obscuration event based on the solar irradiance-passing characteristic of the cloud.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 20, 2013
    Inventors: Yi Yao, Peter Tu, Ming-Ching Chang, Li Guan, Yan Tong
  • Publication number: 20130138499
    Abstract: An advertising system is disclosed. In one embodiment, the system includes an advertising display configured to provide an advertisement to potential customers and a camera configured to capture images of the potential customers when the potential customers pass the advertising display. The system may also include an image processing system having a processor and a memory. The memory may include application instructions for execution by the processor, and the image processing system may be configured to execute the application instructions to derive usage characteristics of the potential customers with respect to the advertising display through analysis of the captured images. Additional methods, systems, and articles of manufacture are also disclosed.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: General Electric Company
    Inventors: Peter Henry Tu, Mark Lewis Grabb, Xiaoming Liu, Ting Yu, Yi Yao, Dashan Gao, Ming-Ching Chang
  • Publication number: 20130138505
    Abstract: An advertising system is disclosed. In one embodiment, the system includes a processor and a memory including application instructions for execution by the processor. The application instructions may include a visual analytics engine to analyze visual information including human activity and a content engine separate from the visual analytics engine to provide advertising content to one or more potential customers. Further, the instructions may include an interface module to enable information generated from analysis of the human activity by the visual analytics engine to be transferred to the content engine in accordance with a specification in which the information generated is characterized with a hierarchical, object-oriented data structure. Additional methods, systems, and articles of manufacture are also disclosed.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: General Electric Company
    Inventors: Peter Henry Tu, Mark Lewis Grabb, Xiaoming Liu, Ting Yu, Yi Yao, Dashan Gao, Ming-Ching Chang
  • Publication number: 20130054377
    Abstract: An advertising system is disclosed. In one embodiment, the system includes an advertising station including a display and configured to provide advertising content to potential customers via the display and one or more cameras configured to capture images of the potential customers when proximate to the advertising station. The system may also include a data processing system to analyze the captured images to determine gaze directions and body pose directions for the potential customers, and to determine interest levels of the potential customers in the advertising content based on the determined gaze directions and body pose directions. Various other systems, methods, and articles of manufacture are also disclosed.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Inventors: Nils Oliver Krahnstoever, Peter Henry Tu, Ming-Ching Chang, Weina Ge
  • Patent number: 8273632
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Ming-Ching Chang, Yih-Ann Lin, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Publication number: 20120108046
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 3, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu Chao Lin, Ming-Ching Chang, Yih-Ann Lin, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Publication number: 20120095582
    Abstract: The present disclosure provides a method of chamber match. The method includes identifying a golden chamber designed operable to implement a semiconductor process; identifying a reference chamber designed operable for the semiconductor process; and extracting a matching index of a processing chamber relative to the golden chamber and the reference chamber using a dynamic variable analysis.
    Type: Application
    Filed: October 15, 2010
    Publication date: April 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bing-Hung Chen, Ming-Ching Chang
  • Patent number: 8053323
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: November 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Ming-Ching Chang, Yih-Ann Lin, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Patent number: 7989355
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: August 2, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Shinn-Sheng Yu, Anthony Yen, Ming-Ching Chang, Jeff J. Xu
  • Publication number: 20100203734
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element.
    Type: Application
    Filed: February 12, 2009
    Publication date: August 12, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Feng Shieh, Shinn-Sheng Yu, Anthony Yen, Ming-Ching Chang, Jeff J. Xu
  • Patent number: 7109085
    Abstract: A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: September 19, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiang-Bau Wang, Li-Te Lin, Ming-Ching Chang, Ryan Chia-Jen Chen, Yuan-Hung Chiu, Hun-Jan Tao
  • Publication number: 20060154487
    Abstract: A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
    Type: Application
    Filed: January 11, 2005
    Publication date: July 13, 2006
    Inventors: Shiang-Bau Wang, Li-Te Lin, Ming-Ching Chang, Ryan Chen, Yuan-Hung Chiu, Hun-Jan Tao
  • Publication number: 20050106888
    Abstract: An integrated process flow including a plasma step for removing oxide residues following oxygen ashing of a photoresist layer is disclosed. The oxide removal step is effective in preventing micro mask defects and is preferably performed in the same process chamber used for the oxygen ashing step and for a subsequent plasma etch used for pattern transfer. The oxide removal step takes less than 60 seconds and involves a halogen containing plasma that is generated from one or more of NF3, Cl2, CF4, CH2F2, and SF6. Optionally, HBr or a fluorocarbon CXFYHZ where x and y are integers and z is an integer or is equal to 0 may be used alone or with one of the aforementioned halogen containing gases. The oxide removal step may be incorporated in a variety of applications including a damascene scheme, shallow trench (STI) fabrication, or formation of a gate electrode in a transistor.
    Type: Application
    Filed: November 14, 2003
    Publication date: May 19, 2005
    Inventors: Yuan-Hung Chiu, Ming-Ching Chang, Hun-Jan Tao
  • Patent number: 6864174
    Abstract: A method for compensating for CD variations across a semiconductor process wafer surface in a plasma etching process including providing a semiconductor wafer having a process surface including photolithographically developed features imaged from a photomask; determining a first dimensional variation of the features with respect to corresponding photomask dimensions along at least one wafer surface direction to determine a first levelness of the process surface; determining gas flow parameters in a plasma reactor for a plasma etching process required to approach a level process surface by reference to an archive of previous plasma etching process parameters carried out in the plasma reactor; carrying out the plasma etching process in the plasma rector according to the determined gas flow parameters; and, determining a second dimensional variation of the features along the at least one wafer surface direction to determine a second levelness of the process surface.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: March 8, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Li-Te S. Lin, Yui Wang, Ming-Ching Chang, Li-Shung Chen, Huain-Jelin Lin, Yuan-Hong Chin, Hong-Yuan Tao
  • Publication number: 20050032386
    Abstract: A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are reduced to complete a polysilicon etching process and an in-situ plasma treatment with an inert gas plasma is carried out prior to neutralize an electrical charge imbalance prior to carrying out an overetch step.
    Type: Application
    Filed: August 4, 2003
    Publication date: February 10, 2005
    Inventors: Ming-Ching Chang, Li-Te Lin, Yu-I Wang, Yuan-Hung Chiu, Hui-Jan Tao
  • Publication number: 20040185584
    Abstract: A method for compensating for CD variations across a semiconductor process wafer surface in a plasma etching process including providing a semiconductor wafer having a process surface including photolithographically developed features imaged from a photomask; determining a first dimensional variation of the features with respect to corresponding photomask dimensions along at least one wafer surface direction to determine a first levelness of the process surface; determining gas flow parameters in a plasma reactor for a plasma etching process required to approach a level process surface by reference to an archive of previous plasma etching process parameters carried out in the plasma reactor; carrying out the plasma etching process in the plasma rector according to the determined gas flow parameters; and, determining a second dimensional variation of the features along the at least one wafer surface direction to determine a second levelness of the process surface.
    Type: Application
    Filed: March 20, 2003
    Publication date: September 23, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Te S. Lin, Yui Wang, Ming-Ching Chang, Li-Shung Chen, Huain-Jelin Lin, Yuan-Hung Chiu, Hun-Jan Tao
  • Publication number: 20040182822
    Abstract: A method for compensating CD variations across a semiconductor process wafer surface in a plasma etching process including a semiconductor wafer having a process surface comprising patterned features; carrying out a first plasma etching process wherein the semiconductor wafer is heated to at least two selectively controllable temperature zones; determining a first dimensional variation of etched features with respect to reference dimensions over predetermined areas of the process surface including the two selectively controllable temperature zones; determining operating temperatures for the two selectively controllable temperature zones to achieve a targeted dimensional variation change in the first dimensional variation to achieve a desired second dimensional variation; plasma etching the process surface to the desired operating temperatures; and, determining an actual dimensional variation change for use in at least one subsequent plasma etching process.
    Type: Application
    Filed: March 20, 2003
    Publication date: September 23, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Shiun Chen, Ming-Ching Chang, Huan-Just Lin, Li-Te S. Lin, Yung -Hung Chiu, Hun-Jan Tao
  • Patent number: 6794302
    Abstract: A method for compensating CD variations across a semiconductor process wafer surface in a plasma etching process including a semiconductor wafer having a process surface comprising patterned features; carrying out a first plasma etching process wherein the semiconductor wafer is heated to at least two selectively controllable temperature zones; determining a first dimensional variation of etched features with respect to reference dimensions over predetermined areas of the process surface including the two selectively controllable temperature zones; determining operating temperatures for the two selectively controllable temperature zones to achieve a targeted dimensional variation change in the first dimensional variation to achieve a desired second dimensional variation; plasma etching the process surface to the desired operating temperatures; and, determining an actual dimensional variation change for use in at least one subsequent plasma etching process.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: September 21, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Li-Shiun Chen, Ming-Ching Chang, Huan-Just Lin, Li-Te S. Lin, Yung-Hog Chiu, Hun-Jan Tao