Patents by Inventor Ming-Ching Chang

Ming-Ching Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD
    Publication number: 20190067128
    Abstract: A method includes removing a first portion of a dummy gate structure over a first fin while keeping a second portion of the dummy gate structure over a second fin, where removing the first portion forms a first recess exposing the first fin, forming a first gate dielectric material in the first recess and over the first fin, and removing the second portion of the dummy gate structure over the second fin, where removing the second portion forms a second recess exposing the second fin. The method further includes forming a second gate dielectric material in the second recess and over the second fin, the second gate dielectric material contacting the first gate dielectric material, and filling the first recess and the second recess with a conductive material.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Ming-Ching Chang, Bao-Ru Young, Yu Chao Lin
  • IMAGE AND VIDEO CAPTURE ARCHITECTURE FOR THREE-DIMENSIONAL RECONSTRUCTION
    Publication number: 20190066317
    Abstract: The present approach relates to an automatic and efficient motion plan for a drone to collect and save a qualified dataset that may be used to improve reconstruction of 3D models using the acquired data. The present architecture provides an automatic image processing context, eliminating low quality images and providing improved image data for point cloud generation and texture mapping.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Inventors: Ming-Ching Chang, Junli Ping, Eric Michael Gros, Arpit Jain, Peter Henry Tu
  • Cut Metal Gate with Slanted Sidewalls
    Publication number: 20190067277
    Abstract: A semiconductor device includes a substrate, first and second fins protruding out of the substrate, and first and second high-k metal gates (HK MG) disposed over the first and second fins, respectively. From a top view, the first and second fins are arranged lengthwise along a first direction, the first and second HK MG are arranged lengthwise along a second direction generally perpendicular to the first direction, and the first and second HK MG are aligned along the second direction. In a cross-sectional view cut along the second direction, the first HK MG has a first sidewall that is slanted from top to bottom towards the second HK MG, and the second HK MG has a second sidewall that is slanted from top to bottom towards the first HK MG. Methods for producing the semiconductor device are also disclosed.
    Type: Application
    Filed: February 26, 2018
    Publication date: February 28, 2019
    Inventors: Ya-Yi Tsai, Chun-Liang Lai, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • THREE-DIMENSIONAL MODELING OF AN OBJECT
    Publication number: 20190066283
    Abstract: The present approach relates to the use of a point cloud of an object to initialize or seed a space carving technique used to generate a 3D model of the object. In one implementation, feature matching is performed on 2D images, with matched features constituting the points of a point cloud model. The point cloud generated in this manner, is one input of a foreground/background segmentation algorithm, which generates a set of segmented 2D images used by a space carving routine to generate a 3D model of the object.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: Eric Michael Gros, Junli Ping, Arpit Jain, Ming-Ching Chang, Peter Henry Tu
  • METAL GATE STRUCTURE CUTTING PROCESS
    Publication number: 20190006345
    Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
    Type: Application
    Filed: November 10, 2017
    Publication date: January 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: SHIANG-BAU WANG, MING-CHING CHANG, SHU-YUAN KU, RYAN CHIA-JEN CHEN
  • Metal Gate Electrode of a Semiconductor Device
    Publication number: 20180350966
    Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 6, 2018
    Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
  • Semiconductor device and method
    Patent number: 10134604
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • SEMICONDUCTOR DEVICE AND METHOD
    Publication number: 20180315618
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Application
    Filed: October 5, 2017
    Publication date: November 1, 2018
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • SYSTEMS AND METHODS FOR ANALYZING TIME SERIES DATA BASED ON EVENT TRANSITIONS
    Publication number: 20180246963
    Abstract: A method for analyzing time series data to identify an event of interest is provided. The method includes receiving, at a computing device, time series data that includes the event of interest, identifying, using the computing device, a start time of the event of interest and an end time of the event of interest by modeling at least one transitional pattern in the time series data, and categorizing, using the computing device, the event of interest based on the at least one transitional pattern.
    Type: Application
    Filed: April 27, 2018
    Publication date: August 30, 2018
    Inventors: Jixu Chen, Peter Henry Tu, Ming-Ching Chang, Yelin Kim, Siwei Lyu
  • Methods for Removing Particles from Etching Chamber
    Publication number: 20180226235
    Abstract: A method includes forming a coating layer in a dry etching chamber, placing a wafer into the dry etching chamber, etching a metal-containing layer of the wafer, and moving the wafer out of the dry etching chamber. After the wafer is moved out of the dry etching chamber, the coating layer is removed.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Yu Chao Lin, Yuan-Ming Chiu, Ming-Ching Chang, Hsin-Yi Tsai, Chao-Cheng Chen
  • Method of Forming an Integrated Circuit
    Publication number: 20180218904
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: August 2, 2018
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Method of making a FinFET device
    Patent number: 10037993
    Abstract: A semiconductor device includes a semiconductor substrate; an isolation region over the semiconductor substrate; and two fin features over the semiconductor substrate and protruding above the isolation region. The two fin features are generally aligned along their longitudinal direction. The device further includes two gate structures disposed over a top surface of the isolation region and engaging top surface and sidewalls of the two fin features respectively. The device further includes source and drain features disposed over the fin features and on both sides of each of the gate structures. The device further includes a first structure disposed between and protruding above the fin features, wherein a bottom surface of the first structure is below the top surface of the isolation region.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 31, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chih-Han Lin, Chao-Cheng Chen, Jr-Jung Lin, Ming-Ching Chang
  • Metal gate electrode of a semiconductor device
    Patent number: 9991375
    Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
  • Systems and methods for analyzing time series data based on event transitions
    Patent number: 9984154
    Abstract: A method for analyzing time series data to identify an event of interest is provided. The method includes receiving, at a computing device, time series data that includes the event of interest, identifying, using the computing device, a start time of the event of interest and an end time of the event of interest by modeling at least one transitional pattern in the time series data, and categorizing, using the computing device, the event of interest based on the at least one transitional pattern.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: May 29, 2018
    Assignee: Morpho Detection, LLC
    Inventors: Jixu Chen, Peter Henry Tu, Ming-Ching Chang, Yelin Kim, Siwei Lyu
  • Method of forming FinFET
    Patent number: 9941407
    Abstract: A method of forming a FinFET is provided. A gate oxide layer and a dummy poly layer are substantially simultaneously etched using an etchant having a higher selectivity on the gate oxide layer than on the dummy poly layer. The gate oxide layer and the dummy poly layer are intersected with the gate oxide layer over a fin layer of the FinFET.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jr-Jung Lin, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Method of forming an integrated circuit using a patterned mask layer
    Patent number: 9934971
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Methods for removing particles from etching chamber
    Patent number: 9934945
    Abstract: A method includes forming a coating layer in a dry etching chamber, placing a wafer into the dry etching chamber, etching a metal-containing layer of the wafer, and moving the wafer out of the dry etching chamber. After the wafer is moved out of the dry etching chamber, the coating layer is removed.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Yuan-Ming Chiu, Ming-Ching Chang, Hsin-Yi Tsai, Chao-Cheng Chen
  • Composite dummy gate with conformal polysilicon layer for FinFET device
    Patent number: 9923079
    Abstract: A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a gate layer over the gate dielectric layer, wherein the gate layer is formed in a conformal manner. The method includes forming a dummy gate layer over the gate layer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Sheng Huang, Chao-Cheng Chen, Ryan Chia-Jen Chen, Ming-Ching Chang, Tzu-Yen Hsieh
  • METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE
    Publication number: 20180047585
    Abstract: A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.
    Type: Application
    Filed: October 2, 2017
    Publication date: February 15, 2018
    Inventors: Tzu-Yen HSIEH, Ming-Ching CHANG, Chia-Wei CHANG, Chao-Cheng CHEN, Chun-Hung LEE, Dai-Lin WU
  • Method of fabricating a semiconductor structure
    Patent number: 9779963
    Abstract: A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chia-Wei Chang, Chao-Cheng Chen, Chun-Hung Lee, Dai-Lin Wu