Abstract: The present invention provides a chip including an I/O pin and an ESD protection circuit. The ESD protection circuit includes a P-type device and a first diode, wherein the P-type device is coupled between the I/O pin and a ground voltage, and an anode of the first diode is directly connected to the I/O pin. In addition, the ESD protection circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin.

Abstract: A conductor structure includes a first metal layer, a second metal layer, and a controlling layer. The second metal layer is disposed on the first metal layer. A material of the first metal layer and a material of the second metal layer include at least one identical metal element. The controlling layer is disposed between the first metal layer and the second metal layer. A thickness of the controlling layer is less than a thickness of the first metal layer, and the thickness of the controlling layer is less than a thickness of the second metal layer.

Abstract: A lens assembly module is provided and includes: a plurality of lenses, a lens barrel disposed around the lens and including an incident end, where light from the object enters the lens barrel, and an emergent end, where light from the object exits the lens barrel; and a first light shielding film disposed in a mounting recess, which is defined by a surface of one of the lenses closest to the emergent end and is adjacent to a circumference of the lens closest to the emergent end.

Abstract: A conductor structure includes a first metal layer, a second metal layer, and a controlling layer. The second metal layer is disposed on the first metal layer. A material of the first metal layer and a material of the second metal layer include at least one identical metal element. The controlling layer is disposed between the first metal layer and the second metal layer. A thickness of the controlling layer is less than a thickness of the first metal layer, and the thickness of the controlling layer is less than a thickness of the second metal layer.

Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.

Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.

Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.

Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.

Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.

Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.

Abstract: A method for transmitting data in real time in a multimedia data stream over a local network is provided. The local network comprises a sending end and one or more receiving ends. The method includes the steps of packaging a QoS (quality of service) control signal into a QoS packet according to a RTCP/TCP/IP protocol; packaging the multimedia data stream into a multimedia data packet according to a RTP/UDP/IP protocol; establishing a connection between the sending end and one of the one or more receiving ends; delivering the QoS packet and the multimedia data packet from the sending end to the one or more receiving end over the local network; and the one or more receiving end de-packaging the QoS packet into the QoS signal to control the transmission of the multimedia data stream.

Abstract: A multipurpose charging system with a transmission function is capable of solving the power consumption problem of a handheld device when the handheld device is connected to a peripheral device. The multipurpose charging system has a handheld device, a transformer device, and a USB line. The handheld device has a built-in USB host chip and a USB socket, and electrically connected to the transformer device by the USB line. The transformer device further has an Ethernet interface and a USB port. The multipurpose charging system can charge the handheld device, supply electric power for a peripheral device connected to the USB port, transmit data, and use an Ethernet by the transformer device at the same time.

Abstract: A method for transmitting data in real time in a multimedia data stream over a local network is provided. The local network comprises a sending end and one or more receiving ends. The method includes the steps of packaging a QoS (quality of service) control signal into a QoS packet according to a RTCP/TCP/IP protocol; packaging the multimedia data stream into a multimedia data packet according to a RTP/UDP/IP protocol; establishing a connection between the sending end and one of the one or more receiving ends; delivering the QoS packet and the multimedia data packet from the sending end to the one or more receiving end over the local network; and the one or more receiving end de-packaging the QoS packet into the QoS signal to control the transmission of the multimedia data stream.

Abstract: A high accurate SOI optical waveguide Michelson interferometer sensor for temperature monitoring combines a waveguide coupler, waveguide, or splitter with two silicon-on-insulator Bragg gratings.

Abstract: A high accurate SOI optical waveguide Michelson interferometer sensor for temperature monitoring has designed and analyzed in this invention. According to the numerical analysis of power reflective spectra of waveguide Michelson interferometers, the temperature sensing of waveguide SOI Michelson interferometer sensor can improve at least 20 times than fiber Bragg grating temperature sensor. Moreover, the SOI Waveguide interferometer sensor we designed presents high sensitivity than pure single waveguide Bragg grating sensor and fiber Bragg grating sensor by adjusting the length of the two interferometric arms. The full wavelength half maximum (FWHM) of our designed SOI optical waveguide Michelson interferometer can be narrowed much smaller than fiber Bragg grating and waveguide Bragg grating sensors for sensitivity improvement. The invention of this optical SOI waveguid sensing devices shows promising results for developing integrated OEIC sensors in the future.

Abstract: A method of determining classification codes for defects occurring in semiconductor processes comparing images of defects from a first selected wafer with images of defects in a first image reference library. The images in the first image reference library are updated from a master image reference library. The images in the master image reference library are the best images of defect types. The images in the master image reference library are in a format readable by all review stations utilized to review the images of the defect.

Abstract: A method of determining an accurate disposition decision for each inspected layer in a wafer lot wherein a measured defect density is compared to a calculated disposition criterion determined for each inspected layer. If the measured defect density is above the calculated disposition criterion the wafer lot is placed on hold and if the measured defect density is at or below the calculated disposition criterion the wafer lot is sent to the next process. The disposition criterion for each layer is determined from a yield value determined for each layer. The yield value is the yield necessary for each layer to obtain a profitable product and is determined from cost data for each die in the wafer lot and a risk factor determined by management and includes market data such as selling price and demand for the product. The yield value is combined with defect sensitivity determined for each layer. The defect sensitivity is determined from the combination of critical area and historical frequency for each layer.

Abstract: A method of manufacturing semiconductor wafers using a simulation tool to determine a set of predicted wafer electrical test parameters. The set of predicted wafer electrical test parameters are compared with wafer electrical test specifications tabulated for each process during the manufacturing process. During the comparison, it is determined whether the predicted wafer electrical test parameters are within the specifications for the process and circuit simulations are then conducted using the predicted wafer electrical test parameters. Device performance is predicted from the circuit simulations and the disposition of the wafer lot is determined utilizing tabulated from a disposition performance table.

Abstract: A method of utilizing associated process data parameters in the manufacture of semiconductor wafers by converting tool-based data to lot based data in order to predict wafer electrical test results from measured in-line critical dimensions, lot based data and the converted tool-based data. The converted tool-based data is obtained by interpolating data between a measurement obtained from a tool at a first time and a measurement obtained from the tool at a second time. The data association is obtained using LaPlace-Everett interpolation. The converted tool-based data can also be obtained by extrapolating data from the historical measurements taken from the tool.

Abstract: A method of manufacturing semiconductor wafers using a simulation tool to determine a set of predicted wafer electrical test measurements that are compared to a set of target wafer electrical test measurements to obtain a set of optimized process parameters for the equipment for the next process. The optimized process parameters are compared to the equipment characteristics for the equipment of the next process and the process parameters for the next process are automatically adjusted.