Patents by Inventor Ming-Dou Ker

Ming-Dou Ker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Substrate-based silicon diode for electrostatic discharge protection
    Publication number: 20070210384
    Abstract: An integrated circuit device is disclosed that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, and a first isolation structure formed inside the well region. Further, a second isolation structure is formed inside the well region and spaced apart from the first isolation structure, a dielectric layer is formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion, and a center portion is disposed between the p-type and n-type portions.
    Type: Application
    Filed: May 4, 2007
    Publication date: September 13, 2007
    Inventors: Chyh-Yih Chang, Ming-Dou Ker
  • High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface
    Publication number: 20070205800
    Abstract: A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.
    Type: Application
    Filed: March 2, 2006
    Publication date: September 6, 2007
    Inventors: Ming-Dou Ker, Wen-Yi Chen, Che-Hao Chuang
  • Level shifter
    Patent number: 7265582
    Abstract: A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by raising the potential of the body terminal of the first input transistor, the threshold voltage is reduced so that the current flowing through the second input transistor is increased to shorten the time of the change of the signal status.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: September 4, 2007
    Assignee: TPO Displays Corp.
    Inventors: Wei-Jen Hsu, Ming-Dou Ker, Ying-Hsin Li, An Shih
  • ON-CHIP LATCH-UP PROTECTION CIRCUIT
    Publication number: 20070188952
    Abstract: An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.
    Type: Application
    Filed: December 29, 2006
    Publication date: August 16, 2007
    Inventors: Ming-Dou Ker, Jang-Jie Peng, Hsin-Chin Jiang
  • Charge-device model electrostatic discharge protection using active device for CMOS circuits
    Patent number: 7253453
    Abstract: An integrated circuit for providing electrostatic discharge protection that includes a contact pad, a CMOS device including a transistor having a substrate, and a CDM clamp for providing electrostatic discharge protection coupled between the contact pad and the CMOS device, the CDM clamp including at least one active device, wherein the CDM clamp conducts electrostatic charges accumulated in the substrate of the transistor to the contact pad and wherein the CMOS device is coupled between a high voltage line and a low voltage line.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: August 7, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Dou Ker, Tang-Kui Tseng, Hsin-Chin Jiang
  • On-chip latch-up protection circuit
    Patent number: 7253999
    Abstract: An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: August 7, 2007
    Inventors: Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang
  • ESD PROTECTION CIRCUIT WITH FEEDBACK TECHNIQUE
    Publication number: 20070171587
    Abstract: The present invention provides ESD protection circuits. The circuit includes: a resistor, a capacitance, a first transistor, an inverter set, and a second transistor. The resistor is connected between a first voltage and node N1. The capacitor is connected between node N1 and a second voltage. The first transistor has a first terminal coupled to the first voltage, a second terminal coupled to the second voltage, and a third terminal coupled to node N2. The inverter set has an input terminal coupled to node N1 and an output terminal coupled to node N2. The second transistor has a first terminal coupled to a first inverter of the inverter set, a second terminal coupled to the second voltage, and a third terminal coupled to an output terminal of a second inverter of the inverter set. The output terminals of the first and the second inverters correspond to opposite logic levels.
    Type: Application
    Filed: January 26, 2006
    Publication date: July 26, 2007
    Inventors: Chien-Ming Lee, Ming-Dou Ker
  • Turn-on-efficient bipolar structures with deep N-well for on-chip ESD protection
    Patent number: 7244992
    Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: July 17, 2007
    Inventors: Ming-Dou Ker, Che-Hao Chuang
  • ESD protection unit with ability to enhance trigger-on speed of low voltage triggered PNP
    Patent number: 7242561
    Abstract: The invention relates to an ESD protection with ability to enhance trigger-on speed of a low voltage Triggered PNP (LVTPNP) unit for protecting internal circuits of an integrated circuit from attack of an ESD stress. The ESD protection unit incorporates either detection circuit or power clamp circuit to efficiently trigger on a trigger node as a heavily doped region of LVTPNP devices among an I/O pad, a VDD pin and a VSS pin. As soon as the trigger node of each LVTPNP device receives a trigger signal from either the ESD detection circuit or power clamp circuit, the threshold voltage of the LVTPNP devices are capable of being therefore reduced to enhance trigger-on speed of the LVTPNP devices that discharge ESD current.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: July 10, 2007
    Assignee: Silicon Integrated System Corp.
    Inventors: Ming-Dou Ker, Chein-Ming Lee
  • Devices without current crowding effect at the finger's ends
    Publication number: 20070152275
    Abstract: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.
    Type: Application
    Filed: February 28, 2007
    Publication date: July 5, 2007
    Inventors: Ming-Dou Ker, Geeng-Lih Lin, Hsin-Chyh Hsu
  • Devices without current crowding effect at the finger's ends
    Publication number: 20070145418
    Abstract: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.
    Type: Application
    Filed: February 28, 2007
    Publication date: June 28, 2007
    Inventors: Ming-Dou Ker, Geeng-Lih Lin, Hsin-Chyh Hsu
  • NOVEL POLY DIODE STRUCTURE FOR PHOTO DIODE
    Publication number: 20070138589
    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.
    Type: Application
    Filed: December 29, 2006
    Publication date: June 21, 2007
    Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang
  • NOVEL POLY DIODE STRUCTURE FOR PHOTO DIODE
    Publication number: 20070126073
    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.
    Type: Application
    Filed: December 29, 2006
    Publication date: June 7, 2007
    Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang
  • POLYDIODE STRUCTURE FOR PHOTO DIODE
    Publication number: 20070114582
    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.
    Type: Application
    Filed: October 2, 2006
    Publication date: May 24, 2007
    Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang
  • High voltage ESD circuit by using low-voltage device with substrate-trigger and gate-driven technique
    Publication number: 20070103825
    Abstract: An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit and a trigger current generating circuit. The trigger current generating circuit will generate trigger signal(s) to turn on the stacked MOS circuit under ESD stress condition. The ESD voltage can thus be discharged through the current path formed by the stacked MOS circuit. A lower trigger voltage is achieved by technologies disclosed, which will make an integrated circuit more sensitive to ESD.
    Type: Application
    Filed: November 9, 2005
    Publication date: May 10, 2007
    Applicant: Silicon Integrated Systems Corp.
    Inventors: Ming-Dou Ker, Chien-Ming Lee
  • Polydiode structure for photo diode
    Patent number: 7205641
    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: April 17, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang
  • ESD protection circuit
    Publication number: 20070030610
    Abstract: An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit, and a trigger current generator. The object of the stacked MOS circuit is to be the first releasing path of the ESD current; the object of the trigger current generator is to generate the trigger current to turn on the stacked MOS circuit, and then the stacked MOS circuit would be the first releasing path of the ESD current.
    Type: Application
    Filed: November 17, 2005
    Publication date: February 8, 2007
    Applicant: SILICON INTEGRATED SYSTEMS CORP.
    Inventors: Ming-Dou Ker, Chien-Ming Lee
  • Uniform turn-on design on multiple-finger MOSFET for ESD protection application
    Patent number: 7170726
    Abstract: An electrostatic discharge protection circuit. The electrostatic discharge (ESD) circuit utilizes inductors and resistors added to sources of multiple fingers of the NMOS transistor, which is triggered by some feedback circuit uniformly. When under an ESD zapping, a finger MOS transistor is trigger initially to snapback region owing to its layout or other causes, a voltage drop across the inductor or the resistor connected to the source of the finger MOS transistor is occurred and presented to gates of the other finger MOS transistors by the feedback circuit. Thus, the other finger MOS transistors are turned on.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: January 30, 2007
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Ming-Dou Ker, Che-Hao Chuang, Wen-Yu Lo
  • Initial-on SCR device for on-chip ESD protection
    Publication number: 20070018193
    Abstract: A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.
    Type: Application
    Filed: July 21, 2005
    Publication date: January 25, 2007
    Inventors: Ming-Dou Ker, Shih-Hung Chen, Kun-Hsien Lin
  • Closed ring structure of electrostatic discharge circuitry
    Publication number: 20070013290
    Abstract: An electrostatic discharge (ESD) circuitry bus within closed ring is disclosed. The closed ring comprises a plurality of metal layer. A metal layer can conduct electricity to another metal layer by conductive plugs. An oxide region can separate the closed ring into two closed ring regions by payout. Each closed ring region does not conduct electricity to each other by an oxide region. One closed ring section is Vdd bus. Therefore, the closed ring of the present invention can be sued by Vss bus and Vdd bus at the same time.
    Type: Application
    Filed: January 13, 2006
    Publication date: January 18, 2007
    Inventors: Ming-Dou Ker, Chien-Ming Lee