Patents by Inventor Ming-Dou Ker

Ming-Dou Ker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TRANSIENT TO DIGITAL CONVERTERS
    Publication number: 20090231765
    Abstract: A digital converter including a first adjustment unit and a first transient detection unit. The first adjustment unit adjusts amplitude of an electrostatic discharge (ESD) pulse to generate a first adjustment signal when an ESD event occurs in a first power line and a second power line is at a complementary level. The first transient detection unit generates a first digital code according to the first adjustment signal.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 17, 2009
    Applicants: HIMAX TECHNOLOGIES LIMITED, NATIONAL CHIAO-TUNG UNIVERSITY
    Inventors: Ming-Dou Ker, Cheng-Cheng Yen, Chi-Sheng Liao, Tung-Yang Chen
  • ESD detection circuit
    Patent number: 7586721
    Abstract: An ESD detection circuit which includes: a triggering circuit for generating an ESD trigger signal when the ESD detection circuit is in ESD mode; a bias circuit for providing at least a first bias voltage and a second bias voltage for controlling the operation of the triggering circuit; a trigger controlling circuit for decreasing a voltage difference between the first bias voltage and the second bias voltage when the ESD detection circuit is in the ESD mode, and for controlling a duration of the ESD trigger signal that is generated by the triggering circuit; and an activating control circuit for activating the trigger controlling circuit and the triggering circuit to enter the ESD mode according to a voltage level at a first node.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: September 8, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Tzu Wang, Ming-Dou Ker
  • Silicon controlled rectifier
    Patent number: 7582916
    Abstract: A silicon controlled rectifier structure of polygonal layouts is provided. The polygonal first conductive type doped region is located in the middle of the polygonal second conductive type well. The first conductive type well shaped as a polygonal ring surrounds the second conductive type well and the second conductive type doped region is located within the first conductive type well and shaped as a polygonal ring concentric to the first conductive type well.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: September 1, 2009
    Assignee: United Microelectronics Corp.
    Inventors: MIng-Dou Ker, Chun-Yu Lin, Chang-Tzu Wang
  • ESD protection for high-voltage-tolerance open-drain output pad
    Publication number: 20090213508
    Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.
    Type: Application
    Filed: January 22, 2009
    Publication date: August 27, 2009
    Inventors: Wu-Tsung Hsihe, Ming-Chun Chou, Ming-Dou Ker
  • Devices without current crowding effect at the finger's ends
    Patent number: 7579658
    Abstract: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: August 25, 2009
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ming-Dou Ker, Geeng-Lih Lin, Hsin-Chyh Hsu
  • INPUT STAGE FOR MIXED-VOLTAGE-TOLERANT BUFFER WITH REDUCED LEAKAGE
    Publication number: 20090195269
    Abstract: A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled to the first circuit through a first node and to the second circuit through a second node. The input circuit includes a first part coupled to the first node and an inverter coupled to the second node. The first part provides a signal having a voltage level approximately equal to the third power supply voltage to the inverter in response to a first signal on the first node, and provides a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node.
    Type: Application
    Filed: March 16, 2009
    Publication date: August 6, 2009
    Inventors: Che-Hao Chuang, Ming-Dou Ker
  • TRANSIENT DETECTION CIRCUIT FOR ESD PROTECTION
    Publication number: 20090187361
    Abstract: A transient detection circuit including a detecting unit, a setting unit, and a memory unit. The transient detection circuit provides an information signal to an external instrument when an electrostatic discharge (ESD) event occurs. The detecting unit is coupled between a first power line and a second power line for detecting the ESD event. The setting unit sets a level of a first node according to the detection result. The memory unit controls the information signal according to the level of the first node. The information signal is at a first level when the ESD event occurs in the first power line.
    Type: Application
    Filed: January 23, 2008
    Publication date: July 23, 2009
    Applicants: HIMAX TECHNOLOGIES LIMITED, NATIONAL CHIAO-TUNG UNIVERSITY
    Inventors: Ming-Dou Ker, Cheng-Cheng Yen, Chi-Sheng Liao, Tung-Yang Chen
  • High/low voltage tolerant interface circuit and crystal oscillator circuit
    Patent number: 7564317
    Abstract: A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: July 21, 2009
    Assignee: Amazing Microelectronic Corporation
    Inventors: Ming-Dou Ker, Hung-Tai Liao, Ryan Hsin-Chin Jiang
  • ESD PROTECTION DESIGN FOR LOW CAPACITANCE SPECIFICATION
    Publication number: 20090180224
    Abstract: An ESD protection circuit with low capacitance, which utilizes ESD protection design for low capacitance specification, includes: an ESD detection circuit, coupled between a first voltage source and a second voltage source, for detecting an ESD voltage to generate a trigger signal; and an ESD protection device, having an end coupled to one of the first voltage source and the second voltage source, and another end coupled to a pad, wherein the ESD protection device performs an ESD protection according to the trigger signal.
    Type: Application
    Filed: January 15, 2008
    Publication date: July 16, 2009
    Inventors: Ming-Dou Ker, Chun Huang, Yuh-Kuang Tseng
  • SILICON CONTROLLED RECTIFIER
    Publication number: 20090179222
    Abstract: A silicon controlled rectifier structure of polygonal layouts is provided. The polygonal first conductive type doped region is located in the middle of the polygonal second conductive type well. The first conductive type well shaped as a polygonal ring surrounds the second conductive type well and the second conductive type doped region is located within the first conductive type well and shaped as a polygonal ring concentric to the first conductive type well.
    Type: Application
    Filed: January 14, 2008
    Publication date: July 16, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Dou Ker, Chun-Yu Lin, Chang-Tzu Wang
  • Liquid Crystal Display Apparatus and Bandgap Reference Circuit Thereof
    Publication number: 20090167663
    Abstract: A liquid crystal display apparatus comprises a system-on-glass (SOG) and a bandgap reference (BGR) circuit. The BGR circuit, which is formed on the SOG, comprises a current mirror set and a diode set. The current mirror set is configured to generate a plurality of fixed currents. The diode set, which is formed by a plurality of diode-connected thin film transistors (TFT), is configured to generate a BGR voltage according to the fixed currents.
    Type: Application
    Filed: April 14, 2008
    Publication date: July 2, 2009
    Applicant: AU OPTRONICS CORP.
    Inventors: Ming-Dou Ker, Hsiao-Wen Zan, Ting-Chou Lu
  • Electrostatic discharge protection device and method of manufacturing the same
    Patent number: 7554159
    Abstract: An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: June 30, 2009
    Inventors: Ming-Dou Ker, Tang-Kui Tseng, Hsin-Chin Jiang, Chyh-Yih Chang, Jeng-Jie Peng
  • Silicon controlled rectifier for the electrostatic discharge protection
    Patent number: 7542253
    Abstract: The present invention relates to an SCR (Silicon Controlled Rectifier) for the ESD (electrostatic discharge) protection comprising two terminal electrodes of a first electrode and a second electrode, a PMOS, an NMOS and an SCR structure. By utilizing an embedded SCR, a whole-chip ESD protection circuit design can be obtained. The present invention is suitable for IC products, and for applications by IC design industries and IC foundry industries.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: June 2, 2009
    Assignee: National Chiao Tung University
    Inventors: Ming-Dou Ker, Kun-Hsien Lin
  • Power-rail ESD protection circuit with ultra low gate leakage
    Publication number: 20090135533
    Abstract: An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
    Type: Application
    Filed: November 28, 2007
    Publication date: May 28, 2009
    Inventors: Ming-Dou Ker, Chin-Hao Chen, Ryan Hsin-Chin Jiang
  • Mixed-voltage input/output buffer
    Patent number: 7532047
    Abstract: A mixed-voltage I/O buffer comprises an input circuit, an output circuit, an I/O pad, a pre-driver circuit coupled to the output circuit, two added coupled N-type transistors, and a dynamical gate-controlled circuit coupled to each gate of the two N-type transistors and the pre-driver circuit; one of the N-type transistors is coupled to the input circuit and the output circuit; the other N-type transistor and the dynamic gate-controlled circuit are together coupled to the I/O pad. Thereby, a mixed-voltage I/O buffer which receives 2×VDD-tolerant input signals and overcomes the hot-carrier degradation is realized.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: May 12, 2009
  • Mixed voltage input/output buffer having low-voltage design
    Patent number: 7532034
    Abstract: A mixed-voltage input/output buffer having low-voltage design comprises a pre-driver, a tracking unit, a driving unit, and input/output pad, a floating-well unit and a transporting unit. The pre-driver receives first data signal and enable signal and outputs first and second data voltages. The tracking unit provides Gate-Tracking function. The driving unit couples the pre-driver and the tracking unit for production of a first buffer voltage corresponding to the first data voltage. The input/output pad couples the driving unit to output a first buffer voltage and to receive a second data signal. The output unit is used for outputting a second buffer voltage corresponding to the second data signal. The floating-well unit couples to the driving unit and the input/output pad in order to output first buffer voltage and receive second data signal. The floating-well unit is used for preventing leakage current.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: May 12, 2009
    Assignee: National Chiao Tung University
    Inventors: Ming-Dou Ker, Shih-Lun Chen
  • Turn-on-efficient bipolar structures for on-chip ESD protection
    Patent number: 7525159
    Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: April 28, 2009
    Inventors: Ming-Dou Ker, Che-Hao Chuang
  • Diode strings and electrostatic discharge protection circuits
    Patent number: 7525779
    Abstract: Diode strings and electrostatic discharge circuits characterized by low current leakage. Each diode region provides a diode and has first and second regions. The first region is of a first conductive type and formed on a substrate, acting as a first electrode of a diode. The second region is of a second conductive type opposite to the first conductive type, formed in the first region and acting as a second electrode of a corresponding diode. The diodes are forward connected in series to form major anode and cathode of the diode string. An isolation region is of the second conductive type to isolate those diode regions. A bias resistor is connected between the isolation region and a first power line. During normal operation, the voltage of the first power line is not within the range between the voltages of the major anode and cathode.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: April 28, 2009
    Inventors: Zi-Ping Chen, Ming-Dou Ker
  • Loading reduction device and method
    Publication number: 20090096432
    Abstract: An active loading-reduction device is provided for a circuit. The circuit has functional circuitry coupled to a terminal to receive an alternating voltage. The circuit also has an electrostatic discharge protector that is coupled to the terminal. The active loading-reduction device includes active circuitry that is adapted to be coupled to a power supply to provide a reactance to counteract a reactance provided by the electrostatic discharge protector at the terminal of the circuit.
    Type: Application
    Filed: October 16, 2007
    Publication date: April 16, 2009
    Inventors: Bo-Shih Huang, Ming-Dou Ker
  • Electrostatic discharge protection for power amplifier in radio frequency integrated circuit
    Patent number: 7518841
    Abstract: A circuit for protecting a power amplifier from electrostatic discharge (ESD) that comprises a clamp circuit connected between a first power line and a connection line, and a detecting circuit connected between the connection line and a second power line for detecting whether an ESD event occurs at a conductive pad coupled to the power amplifier and activating the clamp circuit in response to an ESD event, wherein an ESD current due to the ESD event is conducted by the clamp circuit to the first power line.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: April 14, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Che-Hao Chuang, Ming-Dou Ker