Patents by Inventor Ming-Dou Ker

Ming-Dou Ker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Charge pump circuit suitable for low-voltage process
    Patent number: 7145382
    Abstract: The present invention discloses a charge pump circuit suitable for a low-voltage process. The charge pump circuit is composed of stages of the voltage amplifying circuits connected each other, and the operation of two adjacent stages of voltage amplifying circuit is controlled by two opposite set of the timing signals. Each stage of the voltage amplifying circuit has a coupled pair of a first complementary MOS (CMOS) transistor and a second CMOS transistor switching in accordance with a timing signal and an inverse timing signal inputted into the first and second capacitors. Then, two diode devices guide charges to next stage, and a voltage higher than the integrated circuit voltage source is outputted. The present invention has advantage of high pumping gain, and the reliability issue of the gate oxide layer in the low-voltage process can be also solved.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: December 5, 2006
    Assignee: National Chiao Tung University
    Inventors: Ming-Dou Ker, Chia-Sheng Tsai
  • Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof
    Patent number: 7141484
    Abstract: A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation layer and a silicon layer. The isolating structures are located in the silicon layer to define a well region. The first and second type doped regions are located in the well and are adjacent to the isolating structures. Such a non-gated diode structure can be applied to an electrostatic discharge protection circuit to increase the electrostatic discharge protection voltage or current. In addition, a fabrication method of the non-gated diode is also introduced. This non-gated diode can be also fabricated in the general bulk CMOS process, and used in the on-chip ESD protection circuits.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: November 28, 2006
    Assignee: United Microlectronics Corp.
    Inventors: Ming-Dou Ker, Kei-Kang Hung, Tien-Hao Tang
  • Automatic transmission line pulse system
    Patent number: 7138804
    Abstract: A system for measuring electrostatic discharge (ESD) characteristics of a semiconductor device that comprises at least one pulse generator generating ESD-scale pulses, a first point of the semiconductor device receiving a first ESD-scale pulse from the at least one pulse generator, a second point of the semiconductor device receiving the first ESD-scale pulse from the at least one pulse generator, at least a third point of the semiconductor device receiving a second ESD-scale pulse from the at least one pulse generator, and a data collector to collect data on the ESD characteristics of the semiconductor device.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: November 21, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Dou Ker, Chyh-Yih Chang, Chun-Lin Hou
  • ESD protection circuits with impedance matching for radio-frequency applications
    Publication number: 20060256489
    Abstract: An ESD protection circuit with impedance matching for radio frequency integrated circuits is provided. Nodes at the ends of a transmission line, respectively have at least one ESD component coupled between each and one of the power rails. The ESD components discharge ESD currents and the transmission lines provide RF matching.
    Type: Application
    Filed: May 10, 2005
    Publication date: November 16, 2006
    Inventors: Ming-Dou Ker, Cheng-Ming Lee
  • Electrostatic discharge protection device
    Patent number: 7129546
    Abstract: An ESD protection device. The ESD protection device has a substrate; a channel region, a source region, and a drain region. The channel region is formed on a predetermined area of a surface of the substrate, the channel region has a first side and a second side. The source region is formed adjacent to the first side. The drain region which has a heavily doped region and a lightly doped region formed below the heavily doped region is formed adjacent to the second side. The width along a longitudinal axis of the heavily doped region has variable length and thus the length between one side of the heavily doped region to the second side has variable length.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: October 31, 2006
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ming-Dou Ker, Kun-Hsien Lin, Geeng-Lih Lin
  • ESD protection device with thick poly film and method for forming the same
    Publication number: 20060231896
    Abstract: An ESD protection device with thicker polysilicon film, an electronic apparatus having the same, and a method for manufacturing the same are provided. The ESD protection device can be a diode or a MOS transistor with a thicker polysilicon film employed in an ESD protection circuit to protect an electronic apparatus. The electronic apparatus includes a substrate having a device area and an ESD protection circuit area. A first polysilicon film of a first thickness is formed on the device area of the substrate, so as to form an electronic device. A second polysilicon film of a second thickness is formed on the ESD protection circuit area, so as to form an ESD protection device. The second thickness, which is preferably about in the range of 100 to 500 nanometers, is thicker than the first thickness.
    Type: Application
    Filed: June 13, 2006
    Publication date: October 19, 2006
    Inventors: Ming-Dou Ker, Chih-Kang Deng, Tang-Kui Tseng, An Shih, Sheng-Chieh Yang
  • Level shifter with body-biased circuit
    Patent number: 7123236
    Abstract: A level shifter, with body-biased circuits, is provided for applying in a thin film transistor liquid crystal display (TFT-LCD). The body-biased circuits are configured to bias the bodies of the input terminal transistors of the level shifter so that the threshold voltages of the input terminal transistors are adjustable. This level shifter is capable of operating at a high frequency with low power consumption while a low-level signal is inputting.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: October 17, 2006
    Assignee: TPO Displays Corporation
    Inventors: Ming-Dou Ker, Wen-Hsia Kung, Ya-Hsiang Tai
  • ESD protection circuit and display panel using the same
    Patent number: 7110229
    Abstract: An ESD protection circuit for low temperature poly-silicon thin film transistor panel and a display panel using the same. The feature of the ESD protection circuit comprises an ESD detection circuit disposed between a first power line and a second power line, for outputting an enable signal when an ESD event occurs in the first power line; and a discharge device having a control terminal coupled to the output of the ESD detection circuit, for providing a discharge path between the first and second power lines when the control terminal receives the enable signal.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: September 19, 2006
    Inventors: Sheng-Chieh Yang, An Shih, Ming-Dou Ker, Tang-Kui Tseng
  • High voltage device with ESD protection
    Patent number: 7098522
    Abstract: A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: August 29, 2006
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Geeng-Lih Lin, Yeh-Ning Jou, Ming-Dou Ker
  • ESD protection circuit
    Patent number: 7098511
    Abstract: The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: August 29, 2006
    Assignee: National Chiao Tung University
    Inventors: Ming-Dou Ker, Kun-Hsien Lin
  • Electrostatic discharge protection circuit with active device
    Patent number: 7092227
    Abstract: An electrostatic discharge protection circuit includes a first terminal, a second terminal, an electrostatic discharge device coupled between the first and second terminals, and an active device coupled to the electrostatic discharge device and controlling an electrostatic current through the electrostatic discharge device. The electrostatic discharge device includes at least one of an SCR, an FOD, an active device, a BJT, and an MOS device.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: August 15, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Dou Ker, Tang-Kui Tseng, Hsin-Chin Jiang, Chyh-Yih Chang
  • ESD protection unit with ability to enhance trigger-on speed of low voltage triggered PNP
    Publication number: 20060152868
    Abstract: The invention relates to an ESD protection with ability to enhance trigger-on speed of a low voltage Triggered PNP (LVTPNP) unit for protecting internal circuits of an integrated circuit from attack of an ESD stress. The ESD protection unit incorporates either detection circuit or power clamp circuit to efficiently trigger on a trigger node as a heavily doped region of LVTPNP devices among an I/O pad, a VDD pin and a VSS pin. As soon as the trigger node of each LVTPNP device receives a trigger signal from either the ESD detection circuit or power clamp circuit, the threshold voltage of the LVTPNP devices are capable of being therefore reduced to enhance trigger-on speed of the LVTPNP devices that discharge ESD current.
    Type: Application
    Filed: January 12, 2005
    Publication date: July 13, 2006
    Inventors: Ming-Dou Ker, Chein-Ming Lee
  • Double-triggered silicon controlling rectifier and electrostatic discharge protection circuit thereof
    Patent number: 7071528
    Abstract: A double-triggered silicon controller rectifier (SCR) comprises a plurality of N+ diffusion areas, a plurality of P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: July 4, 2006
    Assignee: National Chiao Tung University
    Inventors: Ming-Dou Ker, Kuo-Chun Hsu
  • ESD protection circuit with tunable gate-bias
    Patent number: 7064942
    Abstract: An ESD protection circuit with tunable gate-bias coupled between a first and second pads for receiving power supply voltages. The ESD protection circuit includes a diode, a resistor coupled between the cathode of the diode and the first pad, a capacitor coupled between the cathode of the diode and the second pad, a first transistor of a first conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the second pad, a second transistor of a second conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the first pad, and a third transistor of the first conductivity type having a gate coupled to the anode of the diode, a drain coupled to the first pad and a source coupled to the second pad.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: June 20, 2006
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Ming-Dou Ker, Wen-Yu Lo
  • Method and structure of diode
    Patent number: 7064418
    Abstract: A method and a structure of a diode are provided. The diode is used in an electrostatic discharge protection circuit using TFT (Thin Film Transistor) fabrication technology. A semiconductor layer is formed on a substrate. A first region of a first carrier concentration is formed in the semiconductor layer. A second region of a second carrier concentration is formed in the semiconductor layer. An insulator is formed on the semiconductor layer. The insulator layer is etched to form at least a contact window. The contact window exposes a portion of an upper surface of the semiconductor layer. A metal layer is formed on the insulator layer. The metal layer fills up the contact window to contact the semiconductor layer.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: June 20, 2006
    Assignee: Toppoly Optoelectronics Corp.
    Inventors: Ying-Hsin Li, Sheng-Chieh Yang, An Shih, Ming-Dou Ker, Tang-Kui Tseng, Chih-Kang Deng
  • Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation
    Patent number: 7049659
    Abstract: A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: May 23, 2006
    Assignee: Silicon Intergrated Systems Corp.
    Inventors: Ming-Dou Ker, Hsin-Chyh Hsu, Wen-Yu Lo
  • Output buffer with low-voltage devices to driver high-voltage signals for PCI-X applications
    Patent number: 7046036
    Abstract: An output buffer circuit with low-voltage devices to driver high-voltage signals for PCI-X applications is proposed. Because power supply voltage of PCI-X is at 3.3V, the high-voltage gate-oxide stress is a serious problem to design PCI-X I/O circuit in a 0.13 ?m 1V/2.5V CMOS process with only low-voltage gate oxide. This proposed output buffer circuit can be operated at 133 MHz in 3.3V PCI-X environment without causing high-voltage gate-oxide reliability problem. In this design, the circuit is implemented in a 0.13 ?m 1V/2.5V CMOS process and the output signal swing can be 3.3V. Besides, a level converter that converts 0V˜1V voltage swing to 1V˜3.3V voltage swing is also presented.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: May 16, 2006
    Assignee: ADMtek Incorporated
    Inventors: Shih-Lun Chen, Ming-Dou Ker
  • Electrostatic discharge protection for power amplifier in radio frequency integrated circuit
    Publication number: 20060092590
    Abstract: A circuit for protecting a power amplifier from electrostatic discharge (ESD) that comprises a clamp circuit connected between a first power line and a connection line, and a detecting circuit connected between the connection line and a second power line for detecting whether an ESD event occurs at a conductive pad coupled to the power amplifier and activating the clamp circuit in response to an ESD event, wherein an ESD current due to the ESD event is conducted by the clamp circuit to the first power line.
    Type: Application
    Filed: November 2, 2004
    Publication date: May 4, 2006
    Inventors: Che-Hao Chuang, Ming-Dou Ker
  • TFT with body contacts
    Patent number: 7038276
    Abstract: A thin-film transistor (TFT) with body contacts is disclosed. It is used in polysilicon TFT LCD's. A body contact region for separating the gate electrode, a source region, and a drain region is made in the TFT. Through the dopants in the body contact region and different impurities in the source region and the drain region, a body-trigger bias is imposed on the body of the TFT. This method reduces the threshold voltage of the TFT driving circuit, thereby increasing the driving current.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: May 2, 2006
    Assignee: Toppoly Optoelectronics Corp.
    Inventors: Ming-Dou Ker, Wen-Hsia Kung, Ya-Hsiang Tai
  • Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation
    Publication number: 20060081927
    Abstract: A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.
    Type: Application
    Filed: November 25, 2005
    Publication date: April 20, 2006
    Inventors: Ming-Dou Ker, Hsin-Chyh Hsu, Wen-Yu Lo