Patents by Inventor Ming-Fu Tsai

Ming-Fu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220302105
    Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 22, 2022
    Inventors: Ming-Fu Tsai, Tzu-Heng Chang, Yu-Ti Su, Kai-Ping Huang
  • Publication number: 20220294212
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.
    Type: Application
    Filed: May 29, 2022
    Publication date: September 15, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Yu-Ti SU, Chia-Wei HSU, Ming-Fu TSAI, Shu-Yu SU, Li-Wei CHU, Jam-Wem LEE, Chia-Jung CHANG, Hsiang-Hui CHENG
  • Publication number: 20220293503
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan TSAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
  • Patent number: 11404409
    Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fu Tsai, Tzu-Heng Chang, Yu-Ti Su, Kai-Ping Huang
  • Publication number: 20220221893
    Abstract: A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.
    Type: Application
    Filed: January 12, 2021
    Publication date: July 14, 2022
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hao Wang, Ting-Chin Cho, Hui-Ting Yang, Yung-Sheng Fang, Igor Elkanovich, Amnon Parnass, Chiung-Chi Lin, Ming-Fu Tsai
  • Publication number: 20220208753
    Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Li-Wei CHU, Ming-Fu TSAI, Jam-Wem LEE, Yu-Ti SU
  • Publication number: 20220208752
    Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Li-Wei CHU, Ming-Fu TSAI, Jam-Wem LEE, Yu-Ti SU
  • Patent number: 11355927
    Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
  • Patent number: 11282831
    Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Jam-Wem Lee, Yu-Ti Su
  • Publication number: 20220029414
    Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 27, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Yu-Ti SU, Chia-Wei HSU, Ming-Fu TSAI, Shu-Yu SU, Li-Wei CHU, Jam-Wem LEE, Chia-Jung CHANG, Hsiang-Hui CHENG
  • Patent number: 10964037
    Abstract: An optical projector module to establish distance to target object in a field of view for three dimensional image acquisition purposes includes a printed circuit board, point light sources mounted on the printed circuit board to emit a plurality of light beams, a lens unit apart from the plurality of point light sources, and a distance adjusting unit connected to the lens unit. A memory storage device is also included. The lens unit comprises separated lenses, the adjusting unit can adjust distances between the lenses of the lens unit, and light beams with a number of light spot patterns can accordingly be projected. Previously-captured images in the memory storage device can be referred to in seeking target objects in the field of view and light beams in different spot-concentrations on or around the target object enable calculations for the capture of images in three dimensions of the target object.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: March 30, 2021
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Yu-Yang Chih, Ming-Fu Tsai, Hsueh-Feng Hsu
  • Patent number: 10957687
    Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
  • Publication number: 20210082906
    Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Li-Wei CHU, Ming-Fu TSAI, Jam-Wem LEE, Yu-Ti SU
  • Publication number: 20210082743
    Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
  • Publication number: 20210066287
    Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Ming-Fu TSAI, Tzu-Heng CHANG, Yu-Ti SU, Kai-Ping HUANG
  • Patent number: 10854501
    Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
  • Patent number: 10840237
    Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fu Tsai, Tzu-Heng Chang, Yu-Ti Su, Kai-Ping Huang
  • Publication number: 20200219868
    Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 9, 2020
    Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
  • Patent number: 10629588
    Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
  • Publication number: 20190379260
    Abstract: An angular position sensing device for detecting angular position of a rotor of a motor includes a first resolver that includes an annular rotor, an annular stator, a plurality of excitation coils and four induction coils. The annular stator has a stator annular body, and a plurality of stator magnetic poles. One of the annular rotor and the annular stator surrounds the other one of the annular rotor and the annular stator. The excitation coils are respectively wound on the stator magnetic poles of the annular stator. The induction coils are respectively wound on four of the stator magnetic poles.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Inventors: MING-FU TSAI, WEI-TE CHUANG, CHIA-HSIANG LIEN, ZHE-WEI ZHANG