Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.

Abstract: In an embodiment, a device includes: a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer over the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD over the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free from the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Abstract: An etchant for etching a cobalt-containing member in a semiconductor structure includes a fluorine-free acid and an alkaline solution, a rate of etching a cobalt-containing member by the etchant is greater than a rate of etching a nitride-containing member by the etchant, and a level of dissolved oxygen of the etchant is less than or equal to 100 ppb. A semiconductor structure, includes a plurality of epitaxial structures over a substrate, a gate structure over the substrate and between two of the plurality of epitaxial structures; a cobalt-containing member over one of the epitaxial structures and adjacent to the gate structure; and a dielectric member over the cobalt-containing member, wherein a top surface of the cobalt-containing member is formed by etching a portion of the cobalt-containing member using an etchant including a fluorine-free acid and an alkaline solution.

Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes second spacers over the semiconductor fin. The second spacers vertically extend farther from the semiconductor fin than the first spacers. The semiconductor device includes a metal gate over the semiconductor fin, the metal gate is sandwiched by the first spacers. The metal gate includes a glue layer that contains tantalum nitride.

Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.

Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

Abstract: A method for processing a substrate is provided. The method includes the following operations: placing a substrate over a first injector in a substrate processing apparatus, the substrate having a front surface and a back surface opposite to the front surface, and the front surface having a plurality of concentric regions; adjusting a temperature of each of the plurality of concentric regions by controlling at least one of a flow rate and a temperature associated with a fluid dispensing from the first injector; and rotating the substrate by a spin base disposed below the substrate, the substrate is rotated with respect to a center axis perpendicular to the front surface thereof when adjusting the temperature. The spin base includes a ring opening for rotating relative to the first injector, and the first injector is displaced from a projection of a center of the substrate from a top view perspective.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Abstract: In an embodiment, a device includes: a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer over the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD over the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free from the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

Abstract: A method of etching a cobalt-containing member in a semiconductor structure includes providing an etchant including a fluorine-free acid and an alkaline solution having a pH value between 8.5 and 13, and etching the cobalt-containing member in the semiconductor structure using the etchant, wherein a rate of etching the cobalt-containing member by the etchant is substantially greater than a rate of etching a nitride-containing member by the etchant. An etchant for etching a cobalt-containing member in a semiconductor structure includes a fluorine-free acid, and an alkaline solution having a pH value between 8.5 and 13; wherein a rate of etching a cobalt-containing member by the etchant is substantially greater than a rate of etching a nitride-containing member by the etchant, and a level of dissolved oxygen of the etchant is substantially less than or equal to 100 ppb.

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

Abstract: A method of forming a semiconductor device includes: forming a semiconductor feature over a substrate, the semiconductor feature includes a conductive region; forming a dielectric layer over the semiconductor feature; patterning the dielectric layer to form a contact opening exposing a top surface of the conductive region; forming a monolayer over the dielectric layer, the top surface of the conductive region remaining exposed; and depositing a conductive material in the contact opening.

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.