Patents by Inventor Ming-Hsi Yeh

Ming-Hsi Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME
    Publication number: 20220115519
    Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 14, 2022
    Inventors: Jian-Jou Lian, Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Po-Yuan Wang, Chieh-Wei Chen
  • Method of breaking through etch stop layer
    Patent number: 11276571
    Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Metal gate using monolayers
    Patent number: 11257924
    Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Chun-Sheng Liang, Ming-Chi Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Hsin-Che Chiang
  • CONNECTING STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20220051982
    Abstract: A connecting structure includes a substrate, a first conductive feature, a second conductive feature, a third conductive feature over the first conductive feature and a fourth conductive feature over the second conductive feature. The substrate includes a first region and a second region. The first conductive feature is disposed in the first region and has a first width. The second conductive feature is disposed in the second region and has a second width greater than the first width of the first conductive feature. The third conductive feature includes a first anchor portion surrounded by the first conductive feature. The fourth conductive feature includes a second anchor portion surrounded by the second conductive feature. A depth difference ratio between a depth of the first anchor portion and a depth of the second anchor portion is less than approximately 10%.
    Type: Application
    Filed: August 11, 2020
    Publication date: February 17, 2022
    Inventors: U-TING CHIU, YU-SHIH WANG, CHUN-CHENG CHOU, YU-FANG HUANG, CHUN-NENG LIN, MING-HSI YEH
  • Controlling Fin-Thinning Through Feedback
    Publication number: 20220045199
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Fin field-effect transistor device and method of forming the same
    Patent number: 11227940
    Abstract: A method of forming a semiconductor device includes removing a dummy gate from over a semiconductor fin; depositing a glue layer and a fill metal over the semiconductor fin; and simultaneously etching the glue layer and the fill metal with a wet etching solution, the wet etching solution etching the glue layer at a faster rate than the fill metal and reshaping the fill metal.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Ming-Hsi Yeh, Chieh-Wei Chen, Tzu-Ang Chiang
  • PATTERNING METHOD AND STRUCTURES RESULTING THEREFROM
    Publication number: 20220013412
    Abstract: A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 13, 2022
    Inventors: Chieh-Wei Chen, Jian-Jou Lian, Tzu-Ang Chiang, Chun-Neng Lin, Ming-Hsi Yeh
  • METAL GATE STRUCTURE AND METHODS THEREOF
    Publication number: 20210398975
    Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.
    Type: Application
    Filed: September 3, 2021
    Publication date: December 23, 2021
    Inventors: Ming-Chi HUANG, Ying-Liang CHUANG, Ming-Hsi YEH, Kuo-Bin HUANG
  • FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME
    Publication number: 20210391455
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Chun-Neng LIN, Jian-Jou LIAN, Ming-Hsi YEH
  • Semiconductor Device and Method
    Publication number: 20210391449
    Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Inventors: Ssu-Yu Liao, Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Fin field-effect transistor device and method of forming the same
    Patent number: 11201084
    Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin protruding above a substrate, where the first dummy gate structure and the second dummy gate structure are surrounded by a dielectric layer; and replacing the first dummy gate structure and the second dummy gate structure with a first metal gate and a second metal gate, respectively, where the replacing includes: removing the first and the second dummy gate structures to form a first recess and a second recess in the dielectric layer, respectively; forming a gate dielectric layer in the first recess and in the second recess; forming an N-type work function layer and a capping layer successively over the gate dielectric layer in the second recess but not in the first recess; and filling the first recess and the second recess with an electrically conductive material.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semicondutor Manufacturing Company, Ltd.
    Inventors: Chieh-Wei Chen, Jian-Jou Lian, Chun-Neng Lin, Tzu-Ang Chiang, Ming-Hsi Yeh
  • Semiconductor Device and Method of Manufacture
    Publication number: 20210384034
    Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.
    Type: Application
    Filed: August 13, 2021
    Publication date: December 9, 2021
    Inventors: Jian-Jou Lian, Li-Min Chen, Neng-Jye Yang, Ming-Hsi Yeh, Shun Wu Lin, Kuo-Bin Huang
  • Semiconductor device and method of forming same
    Patent number: 11195752
    Abstract: A method for forming a semiconductor device includes forming a metal contact on a substrate, forming a first dielectric on the metal contact, forming a first opening in the first dielectric, and performing a wet etch on a bottom surface of the first opening through a first etch stop layer (ESL) over the metal contact. The wet etch forms a first recess in a top surface of the metal contact. An upper width of the first recess is smaller than a lower width of the first recess. A first conductive feature is formed in the first recess and the first opening.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Kuo-Bin Huang, Ming-Hsi Yeh, Po-Nan Yeh
  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
    Publication number: 20210375677
    Abstract: A method for forming a semiconductor device includes forming a metal contact on a substrate, forming a first dielectric on the metal contact, forming a first opening in the first dielectric, and performing a wet etch on a bottom surface of the first opening through a first etch stop layer (ESL) over the metal contact. The wet etch forms a first recess in a top surface of the metal contact. An upper width of the first recess is smaller than a lower width of the first recess. A first conductive feature is formed in the first recess and the first opening.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Yu Shih Wang, Kuo-Bin Huang, Ming-Hsi Yeh, Po-Nan Yeh
  • Gate stack structure and method for forming the same
    Patent number: 11189714
    Abstract: Embodiments of the present disclosure provide a method of cleaning a lanthanum containing substrate without formation of undesired lanthanum compounds during processing. In one embodiment, the cleaning method includes treating the lanthanum containing substrate with an acidic solution prior to cleaning the lanthanum containing substrate with a HF solution. The cleaning method permits using lanthanum doped high-k dielectric layer to modulate effective work function of the gate stack, thus, improving device performance.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chi Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • SUBSTRATE PROCESSING APPARATUS AND METHOD FOR PROCESSING SUBSTRATE
    Publication number: 20210366737
    Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a plurality of holding members and at least a first injector. The plurality of holding members are configured to hold a substrate. The substrate includes a front surface and a back surface opposite to the front surface. The first injector is below the holding members and is configured to face the back surface of the substrate. The first injector is displaced from a projection of a center of the substrate from a top view perspective. A method for processing a substrate is also provided.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 25, 2021
    Inventors: PO-YUAN WANG, TZU ANG CHIANG, JIAN-JOU LIAN, YU SHIH WANG, CHUN-NENG LIN, MING-HSI YEH
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20210351080
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.
    Type: Application
    Filed: February 4, 2021
    Publication date: November 11, 2021
    Inventors: Chun Hsiung TSAI, Yu-Ming LIN, Kuo-Feng YU, Ming-Hsi YEH, Shahaji B. MORE, Chandrashekhar Prakash SAVANT, Chih-Hsin KO, Clement Hsingjen WANN
  • FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME
    Publication number: 20210335613
    Abstract: A method includes forming a gate trench over a semiconductor fin. The gate trench includes an upper portion surrounded by first gate spacers and a lower portion surrounded by second gate spacers and the first gate spacers. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is disposed over a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate electrode overlaying the metal gate in the lower portion of the gate trench, while keeping sidewalls of the first gate spacers and upper surfaces of the second gate spacer overlaid by a second portion of the gate dielectric layer. The method includes removing the second portion of the gate dielectric layer, while remaining the gate electrode substantially intact.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 28, 2021
    Inventors: Tzu Ang CHIANG, Ming-Hsi Yeh, Chun-Neng Lin, Jian-Jou Lian, Po-Yuan Wang, Chieh-Wei CHEN
  • Controlling fin-thinning through feedback
    Patent number: 11158726
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Substrate vapor drying apparatus and method
    Patent number: 11133200
    Abstract: A method of processing a semiconductor substrate is provided. The semiconductor substrate may be placed on a spin chuck with a plurality of holding members, each holding member including a pin having a sloped portion to provide a gap between an upper edge of the substrate and the pin. Thereafter, one or more treatment fluids may be dispensed over the substrate.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Liang Tai, Chun-Hsiang Fan, Kuo-Bin Huang, Ming-Hsi Yeh