Patents by Inventor Ming-Hsi Yeh

Ming-Hsi Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Self-protective layer formed on high-k dielectric layers with different materials
    Patent number: 11114347
    Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a semiconductor device includes a first gate structure and a second gate structure on a substrate; wherein the first gate structure includes a first gate dielectric layer having a first material, and the second gate structure includes a second gate dielectric layer having a second material, the first material being different from the second material, wherein the first and the second gate structures further comprises a first and a second self-protective layers disposed on the first and the second gate dielectric layers respectively, wherein the first self-protective layer comprises metal phosphate and the second self-protective layer comprises boron comprising complex agents and a first work function tuning layer on the first self-protective layer in the first gate structure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Metal gate structure and methods thereof
    Patent number: 11114436
    Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chi Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Fin Field-Effect Transistor Device and Method of Forming the Same
    Publication number: 20210273073
    Abstract: A method of forming a semiconductor device includes removing a dummy gate from over a semiconductor fin; depositing a glue layer and a fill metal over the semiconductor fin; and simultaneously etching the glue layer and the fill metal with a wet etching solution, the wet etching solution etching the glue layer at a faster rate than the fill metal and reshaping the fill metal.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Ming-Hsi Yeh, Chieh-Wei Chen, Tzu-Ang Chiang
  • Semiconductor device and method of manufacture
    Patent number: 11101135
    Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Li-Min Chen, Neng-Jye Yang, Ming-Hsi Yeh, Shun Wu Lin, Kuo-Bin Huang
  • Semiconductor Device and Method of Manufacture
    Publication number: 20210225660
    Abstract: In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Chieh-Wei Chen, Tzu-Ang Chiang, Ming-Hsi Yeh
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210202399
    Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.
    Type: Application
    Filed: July 31, 2020
    Publication date: July 1, 2021
    Inventors: Cheng-Wei CHANG, Chia-Hung CHU, Kao-Feng LIN, Hsu-Kai CHANG, Shuen-Shin LIANG, Sung-Li WANG, Yi-Ying LIU, Po-Nan YEH, Yu Shih WANG, U-Ting CHIU, Chun-Neng LIN, Ming-Hsi YEH
  • Semiconductor Device and Method
    Publication number: 20210202305
    Abstract: In an embodiment, a device includes: a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer over the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD over the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free from the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Po-Nan Yeh, Yu Shih Wang, Ming-Hsi Yeh
  • METHOD OF BREAKING THROUGH ETCH STOP LAYER
    Publication number: 20210202238
    Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.
    Type: Application
    Filed: June 22, 2020
    Publication date: July 1, 2021
    Inventors: Yu Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Self-Protective Layer Formed on High-K Dielectric Layer
    Publication number: 20210193469
    Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.
    Type: Application
    Filed: February 26, 2021
    Publication date: June 24, 2021
    Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • High-k metal gate and method for fabricating the same
    Patent number: 11031302
    Abstract: Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Chih-Long Chiang, Kuo Bin Huang, Ming-Hsi Yeh, Ying-Liang Chuang
  • Gate resistance improvement and method thereof
    Patent number: 11031500
    Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Chun-Sheng Liang, Ming-Hsi Yeh, Ying-Liang Chuang, Hsin-Che Chiang, Chun-Ming Yang, Yu-Chi Pan
  • Semiconductor Device and Method of Manufacture
    Publication number: 20210134660
    Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.
    Type: Application
    Filed: June 19, 2020
    Publication date: May 6, 2021
    Applicants: Taiwan Semiconductor Manufacturing Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Chia-Cheng Chen, Liang-Yin Chen, Ming-Hsi Yeh, Kuo-Bin Huang
  • Wet Cleaning with Tunable Metal Recess for Via Plugs
    Publication number: 20210134662
    Abstract: In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Yu Shih Wang, Shian Wei Mao, Ming-Hsi Yeh, Kuo-Bin Huang
  • FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20210119034
    Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Chieh-Wei Chen, Tzu-Ang Chiang, Ming-Hsi Yeh
  • Self-protective layer formed on high-k dielectric layer
    Patent number: 10937656
    Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20210057282
    Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin protruding above a substrate, where the first dummy gate structure and the second dummy gate structure are surrounded by a dielectric layer; and replacing the first dummy gate structure and the second dummy gate structure with a first metal gate and a second metal gate, respectively, where the replacing includes: removing the first and the second dummy gate structures to form a first recess and a second recess in the dielectric layer, respectively; forming a gate dielectric layer in the first recess and in the second recess; forming an N-type work function layer and a capping layer successively over the gate dielectric layer in the second recess but not in the first recess; and filling the first recess and the second recess with an electrically conductive material.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Chieh-Wei Chen, Jian-Jou Lian, Chun-Neng Lin, Tzu-Ang Chiang, Ming-Hsi Yeh
  • Footing Removal in Cut-Metal Process
    Publication number: 20210057287
    Abstract: A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.
    Type: Application
    Filed: October 19, 2020
    Publication date: February 25, 2021
    Inventors: Ming-Chi Huang, Kuo-Bin Huang, Ying-Liang Chuang, Ming-Hsi Yeh
  • FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20210036145
    Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Chun-Neng Lin, Ming-Hsi Yeh, Hung-Chin Chung, Hsin-Yun Hsu
  • Controlling Fin-Thinning Through Feedback
    Publication number: 20210036130
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Wet cleaning with tunable metal recess for VIA plugs
    Patent number: 10867844
    Abstract: In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu Shih Wang, Shian Wei Mao, Ming-Hsi Yeh, Kuo-Bin Huang