Patents by Inventor Ming Hsiao

Ming Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230317571
    Abstract: An electronic device with a conductive lead having an internal first section and an external second section extending outside a molded package structure, the first section having an obstruction feature extending vertically from a top or bottom side of the conductive lead and engaging a portion of the package structure to oppose movement of the conductive lead outward from the package structure.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Hsiang Ming Hsiao, Hung-Yu Chou, Yuh-Harng Chien, Chih-Chien Ho, Che Wei Tu, Bo-Hsun Pan, Megan Chang
  • Publication number: 20230307241
    Abstract: Recesses may be formed in portions of an ILD layer of a semiconductor device in a highly uniform manner. Uniformity in depths of the recesses may be increased by configuring flows of gases in an etch tool to promote uniformity of etch rates (and thus, etch depth) across the semiconductor device, from semiconductor device to semiconductor device, and/or from wafer to wafer. In particular, the flow rates of gases at various inlets of the etch tool may be optimized to provide recess depth tuning, which increases the process window for forming the recesses in the portions of the ILD layer. In this way, the increased uniformity of the recesses in the portions of the ILD layer enables highly uniform capping layers to be formed in the recesses.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Inventors: Hsu Ming HSIAO, Shen WANG, Kung Shu HSU
  • Publication number: 20230268427
    Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu Ming Hsiao, Ming-Jhe Sie, Hsiu-Hao Tsao, Hong Pin Lin, Che-fu Chen, An Chyi Wei, Yi-Jen Chen
  • Publication number: 20230260790
    Abstract: Spacer layers on sidewalls of a dummy gate structure included in a semiconductor device are trimmed or etched prior to or during a replacement gate process in which the dummy gate structure is replaced with a replacement gate structure. A radical surface treatment operation is performed to etch the spacer layers, which is a type of plasma treatment in which radicals are generated using a plasma. The radicals in the plasma are used to etch the spacer layers such that the shape and/or the geometry of the remaining portions of the spacer layers reduces, minimizes, and/or prevents the likelihood of an antenna defect being formed in the spacer layers and/or in a work function metal layer of the replacement gate structure. This reduces, minimizes, and/or prevents the likelihood of occurrence of damage and/or defects in the replacement gate structure in subsequent processing operations for the semiconductor device.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Hsu Ming HSIAO, Hong Pin LIN
  • Patent number: 11701501
    Abstract: A fluid pressure gun device for a balloon catheter includes a tubular cavity, a fluid tube, a pressure monitoring device, a plunger, a screw structure, a cover and a detent structure, wherein inside the body of the cavity forms a chamber. The plunger is disposed in the chamber, and the inside of the casing forms a chamber. The screwing structure includes two screwing blocks, and each screwing block is oppositely arranged in the chamber according to the plunger as the center. Each of the screw blocks is screwed with the plunger, and a plurality of springs respectively lean against the screw block and the cover. The detent structure is used to depart the screw blocks from the plunger. The plunger is supported by each screw block at least on two opposite sides, and making it a highly reliable combination of the plunger and each screw block.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: July 18, 2023
    Inventor: Ming-Hsiao Lai
  • Patent number: 11664444
    Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsu Ming Hsiao, Ming-Jhe Sie, Hsiu-Hao Tsao, Hong Pin Lin, Che-Fu Chen, An Chyi Wei, Yi-Jen Chen
  • Publication number: 20230147648
    Abstract: This disclosure provides a voltage variable battery cell module having two battery cell groups and an insulative seat. An output anode and an output cathode are embedded in the insulative seat. The battery cell groups are respectively electrically connected to the output anode and the output cathode, and the battery cell groups are connected in series.
    Type: Application
    Filed: March 18, 2022
    Publication date: May 11, 2023
    Inventors: Chueh-Yu KO, Hou-Chi CHEN, Chia-Wen YEN, Ming-Hsiao TSAI
  • Publication number: 20230145017
    Abstract: A battery module includes an insulating base, a pair of electrodes and multiple battery packs. Each electrode is installed to the insulating base and has a bridge portion and a wire connecting part exposed from the insulating base, and a pair of lugs is extended smoothly from each battery pack, and an end of at least a part of the lugs is attached to each bridge portion correspondingly. Therefore, the lug is not being twisted or deformed easily, and the battery module may have good conductive efficiency, long service life, and convenience of changing the battery pack.
    Type: Application
    Filed: March 17, 2022
    Publication date: May 11, 2023
    Inventors: Chueh-Yu KO, Hou-Chi CHEN, Chia-Wen YEN, Ming-Hsiao TSAI
  • Patent number: 11602047
    Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: March 7, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yin-Chen Lin, Ming-Hsiao Ke, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20230060763
    Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Hsu Ming HSIAO, Shen WANG, Kung Shu HSU, Hong LIN, Shiang-Bau WANG, Che-Fu CHEN
  • Patent number: 11424408
    Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 23, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Kuo-Chih Lai, Wei-Ming Hsiao, Hui-Ting Lin, Szu-Yao Yu, Nien-Ting Ho, Hsin-Fu Huang, Chin-Fu Lin
  • Publication number: 20220238632
    Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 28, 2022
    Inventors: Kuo-Chih Lai, Chi-Mao Hsu, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Hsin-Fu Huang
  • Publication number: 20220226621
    Abstract: A fluid pressure gun device for a balloon catheter includes a tubular cavity, a fluid tube, a pressure monitoring device, a plunger, a screw structure, a cover and a detent structure, wherein inside the body of the cavity forms a chamber. The plunger is disposed in the chamber, and the inside of the casing forms a chamber. The screwing structure includes two screwing blocks, and each screwing block is oppositely arranged in the chamber according to the plunger as the center. Each of the screw blocks is screwed with the plunger, and a plurality of springs respectively lean against the screw block and the cover. The detent structure is used to depart the screw blocks from the plunger. The plunger is supported by each screw block at least on two opposite sides, and making it a highly reliable combination of the plunger and each screw block.
    Type: Application
    Filed: January 19, 2021
    Publication date: July 21, 2022
    Inventor: Ming-Hsiao LAI
  • Publication number: 20220133171
    Abstract: A disease diagnosing method and a disease diagnosing system are provided in the disclosure. The disease diagnosing method includes: obtaining continuous images of a body skin and generating a time domain signal according to an average pixel value of a region of interest in each frame of the continuous images; transforming the time domain signal to a frequency domain signal and combining the time domain signal and the frequency domain signal to a time frequency signal; retrieving multiple first features of a first high dimensional space of the time frequency signal to obtain multiple second features of a second high dimensional space; and use the second features as feature vectors to map to a high dimension feature space, and classifying the second features as one of the multiple categories of a disease corresponding to the region of interest in the body skin according to a hyperplane of the high dimension feature space.
    Type: Application
    Filed: October 25, 2021
    Publication date: May 5, 2022
    Applicant: National Taiwan University
    Inventors: Hao-Ming Hsiao, Hsien-Li Kao, Mao-Shin Lin, Chung-Yuan Hsu
  • Publication number: 20220087017
    Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.
    Type: Application
    Filed: July 20, 2021
    Publication date: March 17, 2022
    Inventors: Yin-Chen Lin, Ming-Hsiao Ke, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20220075921
    Abstract: A die layout calculation method is provided. The method includes: selecting, based on a distribution array of a plurality of dies in a wafer, one die as a reference die; making first movements of a wafer center to determine a first coverage region for each first movement, and determining a feasible region based on a number of complete dies in each first coverage region; making a plurality of second movements of the wafer center in the feasible region to determine a second coverage region for each second movement, and determining a relative position of the wafer center in the reference die corresponding to a maximum number of complete dies in the second coverage region; and determining a die layout comprising a location of each die in the wafer. This method improves the accuracy and efficiency of determining the maximum number of dies.
    Type: Application
    Filed: August 12, 2021
    Publication date: March 10, 2022
    Inventors: Li-ming HSIAO, Chen CHEN
  • Publication number: 20220068826
    Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 3, 2022
    Inventors: Chia-Pang Kuo, Chih-Yi Chang, Ming-Hsiao Hsieh, Wei-Hsiang Chan, Ya-Lien Lee, Chien Chung Huang, Chun-Chieh Lin, Hung-Wen Su
  • Publication number: 20210376114
    Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.
    Type: Application
    Filed: March 18, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu Ming Hsiao, Ming-Jhe Sie, Hsiu-Hao Tsao, Hong Pin Lin, Che-fu Chen, An Chyi Wei, Yi-Jen Chen
  • Publication number: 20210351347
    Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Kuo-Chih Lai, Wei-Ming Hsiao, Hui-Ting Lin, Szu-Yao Yu, Nien-Ting Ho, Hsin-Fu Huang, Chin-Fu Lin
  • Patent number: D950680
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: May 3, 2022
    Inventor: Ming-Hsiao Lai