Abstract: A method and apparatus are disclosed for testing the accuracy of images generated by a computer graphics program. An output image created by a graphics program on a particular computer platform is verified by being compared to a reference image, also known as the golden image. The output image is partitioned into several checking apertures where each such checking aperture can be of either a block type or a point type. In either case, each checking aperture is made up of several pixels. One or more attributes of the output image is compared against the reference image upon execution of a test program. For pixels in a point type checking aperture, a positional tolerance is determined. Expected values of pixels in the reference image are then derived by examining the specification of the computer graphics program. The positional tolerances and the expected values, along with color tolerances, are stored in a reference file.

Abstract: A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.

Abstract: An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.

Abstract: A charging circuit includes a programable CPU for supplying a constant voltage and a constant current respectively to a voltage control circuit and a current control circuit so as to obtain function of automatically adjust the charging voltage and fix the current. A voltage checking circuit is provided to coordinate with the CPU for keeping watch of charging operation and checking if a battery being charged is normal or not. If the stored electric volume is less than a quarter (indicating the battery is damaged), if the positive and the negative of the charging circuit are connected reversely with those of the battery, if pinchers of the charging circuit contact each other in a short-circuited condition, or if the pinchers fall off the poles of the battery, the CPU stops at once charging operation so as to protect the charging circuit and batteries.

Abstract: SOI Transistor Having a Self-aligned Body Contact An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

Abstract: An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.

Abstract: An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.

Abstract: Aortic-preferentially-expressed gene-1 (APEG-1) and striated muscle preferentially expressed (SPEG) polypeptide, DNA sequences encoding and controlling the transcription of the APEG-1/SPEG encoding gene, methods of diagnosing vascular injury, methods of conferring smooth muscle-cell specific expression, and methods of inhibiting vascular smooth muscle cell proliferation by increasing the level of APEG-1 at the site of vascular injury.

Abstract: A method of operating a batch sequential machine in a manufacturing plant to optimize processing of lots of work through a plurality of series of processing stations which perform various functions comprising the following steps. Collect interval-times (I.sub.i,j) for processing of lots through individual processing stations. Form a matrix of reduced times for processing lots through the processing stations. Determine permutations of the reduced times for a series of combinations of the processing stations for performing required processing tasks. Select the combination of interval-times providing the maximum reduction of total processing time.

Abstract: An aortic-preferentially-expressed gene-1 (APEG-1) polypeptide, DNA sequences encoding and controlling the transcription of APEG-1, methods of diagnosing vascular injury, and methods of inhibiting vascular smooth muscle cell proliferation by increasing the level of APEG-1 at the site of vascular injury.

Abstract: Modifications of a digital logic device, such as a static or dynamic random access memory (SRAM or DRAM) or pass gate logic circuit or the like, implemented with complementary metal-oxide-semiconductor (CMOS) structures formed with silicon-on-insulator (SOI or, more specifically, SOICMOS) technology effectively suppress transient parasitic bipolar current disturbances (e.g. transient half select write disturb instabilities) caused by a discharge current through a parasitic lateral bipolar transistor formed under the transfer gate field effect transistors. Level shifting of the "off" voltage applied to the gate electrode of the transfer gate transistor dynamically changes the gain of the cell transfer gate to increase memory cell stability without compromising the memory capacity per chip or read/write memory cycle time even though level shifting can greatly increase majority carrier density in the floating body (gate) of a SOICMOS transistor at a particular level shifted voltage range.

Abstract: An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

Abstract: An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.

Abstract: A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.

Abstract: A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.

Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.

Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.

Abstract: A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.

Abstract: A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.

Abstract: In a semiconductor device having two N type regions separated by a P type region, a channel stop is needed to prevent shorting between the two N type regions. The channel stop of the invention has oxide isolators over the two N type regions and a P+ type diffusion lying between the oxide isolators in the P type region. When the N type regions are phosphorus doped deep N- regions biased at different potentials and the P type region is a boron doped P- region, a shallow P+ boron region within the P- region acts as a blocking mechanism to prevent phosphorus from piling up at the semiconductor surface and shorting the two N- regions. The channel stop may be manufactured without adding additional steps to a CMOS process flow. The oxide isolators may be formed when the oxide isolator over the inverse moat separating the P tank and the N tank is created. The P+ region within the channel maybe formed when the sources and drains for transistors within the N tank are formed.