Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. EM rule is kept on the metal segment when a single via is formed over and in contact with the metal segment in the layout. The EM rule is relaxed on the metal segment when two first vias are formed over and in contact with the metal segment in the layout. The two first vias have the same current direction.

Abstract: An electrochemical plating apparatus for depositing a conductive material on a wafer includes a cell chamber. The plating solution is provided from a bottom of the cell chamber into the cell chamber. A plurality of openings passes through a sidewall of the cell chamber. A flow regulator is arranged with each of the plurality of openings configured to regulate an overflow amount of the plating solution flowing out through the each of the plurality of openings. The electrochemical plating apparatus further comprises a controller to control the flow regulator such that overflow amounts of the plating solution flowing out through the plurality of openings are substantially equal to each other.

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

Abstract: Provides an electropolishing treatment method for a stainless steel workpiece, wherein the method comprises the following steps: placing the stainless steel workpiece in an oxalic acid solution and performing supersonic oscillation; performing a first electropolishing treatment to the stainless steel workpiece, wherein the first electropolishing treatment uses the stainless steel workpiece as an anode and 10% to 15% perchloric acid as an electrolyte, and when a constant voltage is set as 12V, the first electropolishing treatment procedure is performed; and performing a second electropolishing treatment to the stainless steel workpiece, wherein the second electropolishing treatment uses the stainless steel workpiece after the first electropolishing treatment as an anode, and an electrolyte consists of ethanol, sulfuric acid and perchloric acid, and when a constant voltage is set as 12V, the second electropolishing treatment is performed to obtain the stainless steel workpiece after the second electropolishing

Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.

Abstract: An assembly includes a cover ring having a first surface and a second surface opposite the first surface, the first surface of the cover ring having a first roughness, and a deposition ring having a first surface facing the cover ring and a second surface opposite the first surface, the first surface of the deposition ring having a second roughness. The first roughness is different from the second roughness.

Abstract: A temperature-sensing device configured to monitor a temperature includes: a first conductive line; a second conductive line, wherein the first and second conductive lines have respective different cross-sectional dimensions; a sensing circuit, coupled to the first and second conductive lines, and configured to determine a logic state of an output signal based on a difference between respective signal levels present on the first and second conductive lines; and a control circuit, coupled to the sensing circuit, and configured to determine whether the monitored temperature is above or below a pre-defined threshold temperature based on the determined logic state.

Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. EM rule is kept on the metal segment when a single via is formed over and in contact with the metal segment in the layout. The EM rule is relaxed on the metal segment when two first vias are formed over and in contact with the metal segment in the layout. The two first vias have the same current direction.

Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.

Abstract: A method of processing a semiconductor wafer is provided. The method includes installing upper lid. The installation of the upper lid includes placing an inlet manifold on a water box; inserting a jig into a lower gas channel in the water box and inserting into an upper gas channel in the inlet manifold; fastening the water box to the inlet manifold; and removing the jig after the water box engaging with the inlet manifold. The method also includes connecting a shower head on a lower side of the water box; and connecting the upper lid to a housing. The method further includes placing a semiconductor wafer into the housing. In addition, the method includes supplying a process gas over the semiconductor wafer through the upper gas channel, the lower gas channel and the shower head.

Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to the current simulation result of the IC. It is determined whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout. The vias are in contact with the metal segment.

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

Abstract: Methods are disclosed herein for fabricating integrated circuit interconnects that can improve electromigration. An exemplary method includes forming a first metal layer of an integrated circuit and forming a second metal layer of the integrated circuit. The first metal layer includes a first conductor electrically coupled to a second conductor, and the second metal layer includes a third conductor electrically coupled to the first conductor. The first conductor, the second conductor, and the third conductor are configured, such that electrons flow from the second conductor to an area of the first conductor where electrons flow from the third conductor to the first conductor.

Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to the current simulation result of the IC. It is determined whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout. The vias are in contact with the metal segment.

Abstract: An electronic device configured to display interactive information is provided, including a communication device, a camera, an input device, a processor and a display. The camera acquires an input image including an image of a display device, and the display device displays an interactive image including a default interaction option. The processor generates a virtual option according to the interactive image and superimposes the virtual option on the input image. The default interaction option and the virtual option correspond to a designated device and a designated service, respectively. The display is configured to display the input image and the virtual option. The processor determines whether the default interaction option or the virtual option is enabled when the input device receives an input operation, so as to provide the designated service in the designated device corresponding to the enabled default interaction option or virtual option.

Abstract: An electronic device configured to display interactive information is provided, including a communication device, a camera, an input device, a processor and a display. The camera acquires an input image including an image of a display device, and the display device displays an interactive image including a default interaction option. The processor generates a virtual option according to the interactive image and superimposes the virtual option on the input image. The default interaction option and the virtual option correspond to a designated device and a designated service, respectively. The display is configured to display the input image and the virtual option. The processor determines whether the default interaction option or the virtual option is enabled when the input device receives an input operation, so as to provide the designated service in the designated device corresponding to the enabled default interaction option or virtual option.

Abstract: A breathing mask includes a mask body unit and a container. The mask body unit includes a mask body having an inner surface configured to cooperate with a user's face to define an interior space therebetween, and two straps respectively connected to two opposite sides of the mask body. The container has a container body defining a chamber for receiving working liquid and formed with a plurality of vent holes for communicating the chamber with the interior space. At least one gas generating unit is connected to the container, and includes an electrolysis device disposed in a casing thereof for electrolyzing the working liquid into a hydrogen/oxygen gas mixture.