Abstract: Methods for tuning threshold voltages of fin-like field effect transistor devices are disclosed herein. An exemplary method includes forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is disposed over a first fin structure, and the second gate structure is disposed over a second fin structure. The method further includes filling the first opening and the second opening by forming a gate dielectric layer, forming a threshold voltage tuning layer over the gate dielectric layer, etching back the threshold voltage tuning layer in the second opening, forming a work function layer over the threshold voltage tuning layer, and forming a metal fill layer over the work function layer. The threshold voltage tuning layer includes tantalum and nitrogen. The etching back uses a tungsten-chloride containing precursor.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.

Abstract: Methods and systems for generating a signature for a device include pre-charging a plurality of conductors to a first voltage level. A voltage leakage for each of the conductors is determined, and a device signature is generating based on the determined leakage.

Abstract: Methods are disclosed herein for fabricating integrated circuit interconnects that can improve electromigration. An exemplary method includes forming a first metal layer of an integrated circuit and forming a second metal layer of the integrated circuit. The first metal layer includes a first conductor electrically coupled to a second conductor, and the second metal layer includes a third conductor electrically coupled to the first conductor. The first conductor, the second conductor, and the third conductor are configured, such that electrons flow from the second conductor to an area of the first conductor where electrons flow from the third conductor to the first conductor.

Abstract: Methods are disclosed herein for fabricating integrated circuit interconnects that can improve electromigration. An exemplary method includes forming a first metal layer of an integrated circuit and forming a second metal layer of the integrated circuit. The first metal layer includes a first conductor electrically coupled to a second conductor, and the second metal layer includes a third conductor electrically coupled to the first conductor. The first conductor, the second conductor, and the third conductor are configured, such that electrons flow from the second conductor to an area of the first conductor where electrons flow from the third conductor to the first conductor.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor devices are disclosed herein. An exemplary method includes forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is disposed over a first fin structure, and the second gate structure is disposed over a second fin structure. The method further includes filling the first opening and the second opening by forming a gate dielectric layer, forming a threshold voltage tuning layer over the gate dielectric layer, etching back the threshold voltage tuning layer in the second opening, forming a work function layer over the threshold voltage tuning layer, and forming a metal fill layer over the work function layer. The threshold voltage tuning layer includes tantalum and nitrogen. The etching back uses a tungsten-chloride containing precursor.

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

Abstract: A temperature-sensing device configured to monitor a temperature includes: a first conductive line; a second conductive line, wherein the first and second conductive lines have respective different cross-sectional dimensions; a sensing circuit, coupled to the first and second conductive lines, and configured to determine a logic state of an output signal based on a difference between respective signal levels present on the first and second conductive lines; and a control circuit, coupled to the sensing circuit, and configured to determine whether the monitored temperature is above or below a pre-defined threshold temperature based on the determined logic state.

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.

Abstract: Methods and systems for generating a signature for a device include pre-charging a plurality of conductors to a first voltage level. A voltage leakage for each of the conductors is determined, and a device signature is generating based on the determined leakage.

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

Abstract: Methods are disclosed herein for fabricating integrated circuit interconnects that can improve electromigration. An exemplary method includes forming a first metal layer of an integrated circuit and forming a second metal layer of the integrated circuit. The first metal layer includes a first conductor electrically coupled to a second conductor, and the second metal layer includes a third conductor electrically coupled to the first conductor. The first conductor, the second conductor, and the third conductor are configured, such that electrons flow from the second conductor to an area of the first conductor where electrons flow from the third conductor to the first conductor.

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

Abstract: An integrated circuit (IC) comprises first and second conductors in one layer of the IC, wherein the first conductor is oriented along a first direction, the second conductor is oriented along a second direction generally perpendicular to the first direction, and the second conductor is electrically connected to the first conductor. The IC further comprises a third conductor in another layer of the IC, oriented along the second direction, and above the second conductor; a first via connecting the first and third conductors; and a second via connecting the second and third conductors.

Abstract: An integrated circuit (IC) comprises a first conductor in one layer of the IC, a second conductor in another layer of the IC, and a first metal plug connecting the first and second conductors. The IC further comprises an atomic source conductor (ASC) in the one layer of the IC and joined to the first conductor, and a second metal plug connecting the ASC to a voltage source of the IC. The first conductor and the ASC are configured to be biased to different voltages so as to establish an electron path from the second metal plug to the first metal plug such that the ASC acts as an active atomic source for the first conductor.

Abstract: An integrated circuit (IC) comprises a first conductor in one layer of the IC, a second conductor in another layer of the IC, and a first metal plug connecting the first and second conductors. The IC further comprises an atomic source conductor (ASC) in the one layer of the IC and joined to the first conductor, and a second metal plug connecting the ASC to a voltage source of the IC. The first conductor and the ASC are configured to be biased to different voltages so as to establish an electron path from the second metal plug to the first metal plug such that the ASC acts as an active atomic source for the first conductor.

Abstract: An integrated circuit (IC) comprises first and second conductors in one layer of the IC, wherein the first conductor is oriented along a first direction, the second conductor is oriented along a second direction generally perpendicular to the first direction, and the second conductor is electrically connected to the first conductor. The IC further comprises a third conductor in another layer of the IC, oriented along the second direction, and above the second conductor; a first via connecting the first and third conductors; and a second via connecting the second and third conductors.

Abstract: A method of checking joule heating of an integrated circuit design, the method includes dividing the integrated circuit design into a plurality of windows, determining a power index of each window, adjusting the specification current value associated with each of the corresponding windows, and generating a current violation report, by a processor, of the integrated circuit. Each window includes one or more circuit elements. Each circuit element is associated with a corresponding current value. Each window is associated with a corresponding specification current value. Each power index is associated with a corresponding window. An amount of adjustment of the specification current value is a function of the power index of each corresponding window. The current violation report includes one or more entries. Each entry is associated with at least a corresponding window and one or more corresponding current values which exceed the corresponding adjusted specification current value.