Patents by Inventor Ming-Hua Yu

Ming-Hua Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Increasing Source/Drain Dopant Concentration to Reduced Resistance
    Publication number: 20190341472
    Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 7, 2019
    Inventors: Yi-Jing Lee, Ming-Hua Yu
  • Epitaxial growth methods and structures thereof
    Patent number: 10453925
    Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang
  • FinFET with rounded source/drain profile
    Patent number: 10388792
    Abstract: A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Chih-Pin Tsao, Pei-Ren Jeng, Tze-Liang Lee
  • Fin field-effect transistors and methods of forming the same
    Patent number: 10355105
    Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Ming-Hua Yu
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE
    Publication number: 20190131310
    Abstract: A semiconductor device includes a transistor, an isolation structure, and a fin sidewall structure. The transistor includes a fin extending from a substrate and an epitaxy structure grown on the fin. The isolation structure is above the substrate. The fin sidewall structure is above the isolation structure and is on a sidewall of the epitaxy structure. A method for manufacturing the semiconductor device is also disclosed.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing LEE, Tsz-Mei KWOK, Ming-Hua YU, Kun-Mu LI
  • FIN FIELD-EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME
    Publication number: 20190131434
    Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 2, 2019
    Inventors: Yi-Jing Lee, Ming-Hua Yu
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190123201
    Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Kun-Mu LI, Tsz-Mei KWOK, Ming-Hua YU, Chan-Lon YANG
  • Semiconductor strips with undercuts and methods for forming the same
    Patent number: 10269937
    Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Tang Peng, Chia-Wei Chang, Ming-Hua Yu, Hao-Ming Lien, Chao-Cheng Chen, Tze-Liang Lee
  • Semiconductor device and method
    Patent number: 10269655
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Lee, Tsung-Hsi Yang, Ming-Hua Yu
  • EPITAXIAL GROWTH METHODS AND STRUCTURES THEREOF
    Publication number: 20190109194
    Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 11, 2019
    Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang
  • METHOD OF FORMING SHAPED SOURCE/DRAIN EPITAXIAL LAYERS OF A SEMICONDUCTOR DEVICE
    Publication number: 20190006491
    Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.
    Type: Application
    Filed: November 1, 2017
    Publication date: January 3, 2019
    Inventors: Yi-Jing LEE, Ming-Hua YU
  • Semiconductor device, static random access memory cell and manufacturing method of semiconductor device
    Patent number: 10170483
    Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu, Kun-Mu Li
  • Metrology system and measurement method using the same
    Patent number: 10163669
    Abstract: A method for thickness measurement includes forming an implantation region in a semiconductor substrate. A semiconductor layer is formed on the implantation region of the semiconductor substrate. Modulated free carriers are generated in the implantation region of the semiconductor substrate. A probe beam is provided on the semiconductor layer and the implantation region of the semiconductor substrate with the modulated free carriers therein. The probe beam reflected from the semiconductor layer and the implantation region is detected to determine a thickness of the semiconductor layer.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Chieh Hung, Ming-Hua Yu, Yi-Hung Lin, Jet-Rung Chang
  • Semiconductor device and manufacturing method thereof
    Patent number: 10164096
    Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Mu Li, Ming-Hua Yu, Tsz-Mei Kwok, Chan-Lon Yang
  • Semiconductor Device Having Merged Epitaxial Features with Arc-Like Bottom Surface and Method of Making the Same
    Publication number: 20180350687
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 6, 2018
    Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
  • SEMICONDUCTOR DEVICE HAVING FINS
    Publication number: 20180342621
    Abstract: A device includes a semiconductor substrate, an isolation structure, and an epitaxial fin portion. The semiconductor substrate has an implanted region. The implanted region has a bottom fin portion thereon, in which a depth of the implanted region is smaller than a thickness of the semiconductor substrate. The isolation structure surrounds the bottom fin portion. The epitaxial fin portion is disposed over a top surface of the bottom fin portion, in which the implanted region of the semiconductor substrate includes oxygen and has an oxygen concentration lower than about 1·E+19 atoms/cm3.
    Type: Application
    Filed: July 13, 2018
    Publication date: November 29, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Yu LIN, Ming-Hua YU, Tze-Liang LEE, Chan-Lon YANG
  • FinFET Device Having Flat-Top Epitaxial Features and Method of Making the same
    Publication number: 20180337182
    Abstract: A semiconductor device and method of forming the same are disclosed. The method of forming a semiconductor device includes providing a substrate, an isolation structure over the substrate, and at least two fins extending from the substrate and through the isolation structure; etching the at least two fins, thereby forming at least two trenches; growing first epitaxial features in the at least two trenches; growing second epitaxial features over the first epitaxial features in a first growth condition; and after the second epitaxial features reach a target critical dimension, growing the second epitaxial features in a second growth condition different from the first growth condition.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 22, 2018
    Inventors: Yi-Jing Lee, Li-Wei Chou, Ming-Hua Yu
  • SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE
    Publication number: 20180315855
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 1, 2018
    Inventors: Eric PENG, Chao-Cheng CHEN, Chii-Horng LI, Ming-Hua YU, Shih-Hao LO, Syun-Ming JANG, Tze-Liang LEE, Ying Hao HSIEH
  • Semiconductor device having merged epitaxial features with Arc-like bottom surface and method of making the same
    Patent number: 10049936
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
  • Fin structure of semiconductor device, manufacturing method thereof, and manufacturing method of active region of semiconductor device
    Patent number: 10026843
    Abstract: A method for manufacturing an active region of a semiconductor device includes forming an implanted region in a substrate. The implanted region is adjacent to a top surface of the substrate. A clean treatment is performed on the top surface of the substrate. The top surface of the substrate is baked. An epitaxial layer is formed on the top surface of the substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: July 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Yu Lin, Ming-Hua Yu, Tze-Liang Lee, Chan-Lon Yang