Abstract: Improved bit error correction for non-volatile memory can be implemented in multiple stages achieving improved correction capacity. As an example, bit error correction for a set of data can utilize a logic or a differential algorithm applied to one or more copies (N) of the set of data to produce a logic (or differential) output. An error correction code (ECC) can be applied to the logic (or differential) output to produce corrected data that corrects bit errors of the set of data, if any, up to a maximum for the ECC selected. An algorithm can be selected to address measured bit error rates or variations in bit error rates among binary bit states of a non-volatile memory.

Abstract: An in-memory computing apparatus and a computing method thereof are provided. A memory array includes a shifted weight storage area that stores shifted weight values, a shift information storage area that stores the number of shift units, and a shift unit amount storage area that stores a shift unit amount. A shift restoration circuit restores a weight shift amount of a shifted sum-of-products according to the number of shift units of the shifted weight values and a column shift unit amount, so as to generate multiple restored sum-of-products.

Abstract: A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.

Abstract: A non-volatile memory device includes a first memory cell array, a first error correction code (ECC) decoder and a controller. The first memory cell array is divided into a first sub-array and a second sub-array by a first address boundary. The first ECC decoder is coupled to the first memory cell array, performs an ECC operation on read-out data from first memory cell array. The controller is coupled to the first memory cell array and the first ECC decoder, adjusts the first address boundary according to a first ECC failure bit number.

Abstract: The disclosure is directed to a memory storage apparatus having a dynamic data repair mechanism. The memory storage apparatus includes a connection interface; a memory array; and a memory control circuit configured at least to: receive, from the connection interface, a write command which includes a user data and an address of the user data; encode the user data as a codeword which includes the user data and parity bits; write the codeword, in a first memory location of the memory array, as a written codeword; perform a read procedure of the written codeword to determine whether the written codeword is erroneously written; and store a redundant codeword of the user data in a second memory location in response to having determined that the written codeword is erroneously written.

Abstract: A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.

Abstract: An encoding method for a memory storage apparatus adopting an ECC algorithm is provided. The memory storage apparatus comprises an ECC encoder. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword; attaching a flip bit to the write data; encoding the write data and the flip bit to generate parity bits based on the ECC algorithm by the ECC encoder and attaching the write data and the flip bit to the plurality of parity bits to generate a new codeword; flipping the new codeword based on a number of bits among selected bits required to be changed from the existing codeword to the new codeword; and writing one of the new codeword and the flipped new codeword to the write address. In addition, a memory storage apparatus using the encoding method is provided.

Abstract: The codeword accessing method including: receiving a write data with M message bits; generating parity information with N-M bits based on an error correction algorithm and the M message bits, where N and M are positive integers; transforming the M message bits and the parity information to a scrambled codeword with N bits by a scrambling operation, where the scrambled codeword contains only a part of the M message bits; and writing the scrambled codeword into a memory device.

Abstract: The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N?1 pre-set error correction number(s), and N is a positive integer larger than 1.

Abstract: The disclosure is directed to a RRAM having a plurality of 1TnR structures. In an aspect, the disclosure provides a RRAM including a plurality of 1TnR structures which includes a first 1TnR structure which includes a first transistor having a first gate terminal connected to a first word line, a first drain terminal, and a first source terminal connected to a source line, wherein the source line is connected to each of the plurality of 1TnR structures; and a first N parallel resistors group including a first resistor and a second resistor which are connected to the first drain terminal and connected to each other in parallel, wherein the first resistor is connected to a first bit line, the second resistor is connected to a second bit line, and N is an integer greater than one.

Abstract: The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N?1 pre-set error correction number(s), and N is a positive integer larger than 1.

Abstract: The codeword accessing method including: receiving a write data with M message bits; generating parity information with N-M bits based on an error correction algorithm and the M message bits, where N and M are positive integers; transforming the M message bits and the parity information to a scrambled codeword with N bits by a scrambling operation, where the scrambled codeword contains only a part of the M message bits; and writing the scrambled codeword into a memory device.

Abstract: A PUF code providing apparatus includes a non-volatile memory cell pair and a data sensing circuit. The sensing circuit is coupled to the non-volatile memory cell pair, reads two initial statuses of the non-volatile memory cell pair and generates a PUF code by comparing the two initial statuses of the non-volatile memory cell pair.

Abstract: The disclosure is directed to a memory storage apparatus having a dynamic data repair mechanism. The memory storage apparatus includes a connection interface; a memory array; and a memory control circuit configured at least to: receive, from the connection interface, a write command which includes a user data and an address of the user data; encode the user data as a codeword which includes the user data and parity bits; write the codeword, in a first memory location of the memory array, as a written codeword; perform a read procedure of the written codeword to determine whether the written codeword is erroneously written; and store a redundant codeword of the user data in a second memory location in response to having determined that the written codeword is erroneously written.

Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword comprising a first flip bit indicating bit-flipping of the existing codeword and flipping bits of the existing codeword based on the first flip bit; encoding the write data into a new codeword based on a Lien Code by an ECC encoder, and flipping bits of the new codeword based on a number of bits required to be changed from the existing codeword to the new codeword; and writing the new codeword comprising a first flip bit indicating bit-flipping of the new codeword to the write address In addition, a memory storage apparatus using the encoding method based on the Lien Code is provided.

Abstract: An encoding method for a memory storage apparatus adopting an ECC algorithm is provided. The memory storage apparatus comprises an ECC encoder. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword; attaching a flip bit to the write data; encoding the write data and the flip bit to generate parity bits based on the ECC algorithm by the ECC encoder and attaching the write data and the flip bit to the plurality of parity bits to generate a new codeword; flipping the new codeword based on a number of bits among selected bits required to be changed from the existing codeword to the new codeword; and writing one of the new codeword and the flipped new codeword to the write address. In addition, a memory storage apparatus using the encoding method is provided.

Abstract: The disclosure is directed to a method and an apparatus for implementing an error correcting code (ECC) used by a memory storage apparatus. In an aspect of the disclosure, the method would include not limited to: receiving a write command having a write address and a write data; reading an existing codeword comprising a predetermined bit sequence; encoding the write data into a new codeword based on a default ECC; flipping at least one bit of the new codeword based on a number of bits required to be changed from the existing codeword to the new codeword; writing the new codeword, wherein in response to every message bit of the new codeword to be flipped once, either an average or a maximum number of parity bits flips of the new codeword is minimized according to a modified ECC which is based on the default ECC.

Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword comprising a first flip bit indicating bit-flipping of the existing codeword and flipping bits of the existing codeword based on the first flip bit; encoding the write data into a new codeword based on a Lien Code by an ECC encoder, and flipping bits of the new codeword based on a number of bits required to be changed from the existing codeword to the new codeword; and writing the new codeword comprising a first flip bit indicating bit-flipping of the new codeword to the write address In addition, a memory storage apparatus using the encoding method based on the Lien Code is provided.

Abstract: A data write method for writing data is provided. The data writing method is adapted to a memory controller adopting an ECC scheme and includes: encoding the data to generate a codeword; writing the codeword into the memory array according to a first write condition; and performing a verify operation. The step of performing the verify operation includes: reading the codeword from the memory array; comparing the read codeword with the codeword and obtaining an error bit number of the read codeword; decoding the read codeword to generate a decoded data by an ECC decoder; comparing the decoded data with the data; and comparing the error bit number of the read codeword with a pass threshold if the decoded data is identical to the data. If the error bit number of the read codeword is greater than the pass threshold, the data write method further comprises writing the codeword into the memory array according to a second write condition, where the second write condition is different from the first write condition.

Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a first data or a second data which is one's complement of the first data; and performing an encoding operation based on the Lien Code by the ECC encoder. The encoding operation includes: if the first data is received, generating a first codeword according to the first data; and if the second data is received, generating a second codeword which is one's complement of the first codeword according to the second data. In addition, a memory storage apparatus using the encoding method based on the Lien Code is also provided.