Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a first data or a second data which is one's complement of the first data; and performing an encoding operation based on the Lien Code by the ECC encoder. The encoding operation includes: if the first data is received, generating a first codeword according to the first data; and if the second data is received, generating a second codeword which is one's complement of the first codeword according to the second data. In addition, a memory storage apparatus using the encoding method based on the Lien Code is also provided.

Abstract: A data write method for writing data is provided. The data writing method is adapted to a memory controller adopting an ECC scheme and includes: encoding the data to generate a codeword; writing the codeword into the memory array according to a first write condition; and performing a verify operation. The step of performing the verify operation includes: reading the codeword from the memory array; comparing the read codeword with the codeword and obtaining an error bit number of the read codeword; decoding the read codeword to generate a decoded data by an ECC decoder; comparing the decoded data with the data; and comparing the error bit number of the read codeword with a pass threshold if the decoded data is identical to the data. If the error bit number of the read codeword is greater than the pass threshold, the data write method further comprises writing the codeword into the memory array according to a second write condition, where the second write condition is different from the first write condition.

Abstract: A PUF code providing apparatus includes a non-volatile memory cell pair and a data sensing circuit. The sensing circuit is coupled to the non-volatile memory cell pair, reads two initial statuses of the non-volatile memory cell pair and generates a PUF code by comparing the two initial statuses of the non-volatile memory cell pair.

Abstract: A data read method for a memory storage device is provided. The data read method includes: receiving a first read command from a host system for reading first data; calculating an error bit number of the first data; and performing a correction of the first data. If the error bit number is not greater than a predetermined number, finishing the correction of the first data and returning the corrected first data at a pre-defined timing. If the error bit number is greater than a predetermined number, finishing the correction of the first data and returning the corrected first data after the pre-defined timing. In addition, a memory storage device using the data read method is also provided.

Abstract: A memory system includes a resistive nonvolatile memory array configured to store data and error correction code (ECC) bits and a memory controller. The memory controller is configured to detect a number of errors among the stored look-ahead bits, compare the number of look-ahead bit errors to a threshold number of bit errors, perform a strong refresh of the data and look-ahead bits stored in the resistive nonvolatile memory array when the number of look-ahead bit errors equals or exceeds the threshold, and perform a weak refresh of the data and look-ahead bits by refreshing only units of stored data having data bit errors and look-ahead bits having look-ahead bit errors when the number of look-ahead bit errors is less than the threshold.

Abstract: A memory system and operating method thereof are provided. The non-volatile memory array is configured to store data. The controller is coupled to the non-volatile memory array. The memory controller is configured to provide a special write operation to write the data in the non-volatile memory array before a board mount operation is applied, and provide a regular write operation to write the data in the non-volatile memory array after the board mount operation is applied. A read margin provided by the special write operation is larger than a read margin provided by the regular write operation.

Abstract: A system includes a first nonvolatile memory array, a second nonvolatile memory array, and a memory controller. The memory controller is configured to write an indicator bit to the second nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events, and write data stored in the second nonvolatile memory array to the first nonvolatile memory array when the indicator bit is valid.

Abstract: A system includes a first nonvolatile memory array, a second nonvolatile memory array, and a memory controller. The memory controller is configured to write an indicator bit to the second nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events, and write data stored in the second nonvolatile memory array to the first nonvolatile memory array when the indicator bit is valid.

Abstract: A system includes a first nonvolatile memory array, a second nonvolatile memory array, and a memory controller. The memory controller is configured to write an indicator bit to the second nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events, and write data stored in the second nonvolatile memory array to the first nonvolatile memory array when the indicator bit is valid.

Abstract: A system includes a first nonvolatile memory array, a second nonvolatile memory array, and a memory controller. The memory controller is configured to write an indicator bit to the second nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events, and write data stored in the second nonvolatile memory array to the first nonvolatile memory array when the indicator bit is valid.

Abstract: A memory system includes a resistive nonvolatile memory array configured to store data and error correction code (ECC) bits and a memory controller. The memory controller is configured to detect a number of errors among the stored look-ahead bits, compare the number of look-ahead bit errors to a threshold number of bit errors, perform a strong refresh of the data and look-ahead bits stored in the resistive nonvolatile memory array when the number of look-ahead bit errors equals or exceeds the threshold, and perform a weak refresh of the data and look-ahead bits by refreshing only units of stored data having data bit errors and look-ahead bits having look-ahead bit errors when the number of look-ahead bit errors is less than the threshold.

Abstract: A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.

Abstract: A non-volatile static random access memory (nvSRAM) circuit is provided. The nvSRAM circuit includes first and second switches and a latch circuit. The first switch has a first terminal coupled to a first bit line. The second switch has a first terminal coupled to a second bit line. The latch circuit is coupled to second terminals of the first and second switches. The latch circuit has a first non-volatile memory element. When the nvSRAM circuit is at a writing mode, first input data on the first bit line is written into in the latch circuit, and the first non-volatile memory element has a first state corresponding to the first data. When the nvSRAM circuit is at a reading mode, first readout data is generated according to the first state of the first non-volatile memory element is generated and provided to the first bit line.

Abstract: A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“IC”) die, and the other being any suitable authentication IC die. Either die may be stacked upon the other, or the die may be placed side-by-side. The external contacts may correspond to the power and signal requirements of the standard nonvolatile memory IC die so that the pin-out of the memory device package may present a standard pinout. The power and signal requirements of the authentication IC die may be satisfied with some or all of the pins for the nonvolatile memory integrated circuit die, or with other unused pins of the device package. One or more additional external contacts may be added exclusively for the authentication integrated circuit die. One or more signals may be dedicated as between the standard nonvolatile memory IC die and the authentication IC die.

Abstract: A resistive memory device is provided. A first cell is coupled to a word line, a first bit line and a source line. A second cell is coupled to the word line, a second bit line and the source line. A control circuit controls the levels of the word line, the first bit line and the source line to execute a set operation for the first cell and execute a reset operation for the second cell. After the set and the reset operations, the resistance of the first cell is less than the resistance of the second cell. During the execution of the set operation, the control circuit asserts the level of the source line at a pre-determined level. During the execution of the reset operation, the control circuit asserts the level of the source line at the pre-determined level.

Abstract: A non-volatile static random access memory (nvSRAM) circuit is provided. The nvSRAM circuit includes first and second switches and a latch circuit. The first switch has a first terminal coupled to a first bit line. The second switch has a first terminal coupled to a second bit line. The latch circuit is coupled to second terminals of the first and second switches. The latch circuit has a first non-volatile memory element. When the nvSRAM circuit is at a writing mode, first input data on the first bit line is written into in the latch circuit, and the first non-volatile memory element has a first state corresponding to the first data. When the nvSRAM circuit is at a reading mode, first readout data is generated according to the first state of the first non-volatile memory element is generated and provided to the first bit line.

Abstract: A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“IC”) die, and the other being any suitable authentication IC die. Either die may be stacked upon the other, or the die may be placed side-by-side. The external contacts may correspond to the power and signal requirements of the standard nonvolatile memory IC die so that the pin-out of the memory device package may present a standard pinout. The power and signal requirements of the authentication IC die may be satisfied with some or all of the pins for the nonvolatile memory integrated circuit die, or with other unused pins of the device package. One or more additional external contacts may be added exclusively for the authentication integrated circuit die. One or more signals may be dedicated as between the standard nonvolatile memory IC die and the authentication IC die.

Abstract: A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.

Abstract: A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“IC”) die, and the other being any suitable authentication IC die. Either die may be stacked upon the other, or the die may be placed side-by-side. The external contacts may correspond to the power and signal requirements of the standard nonvolatile memory IC die so that the pin-out of the memory device package may present a standard pinout. The power and signal requirements of the authentication IC die may be satisfied with some or all of the pins for the nonvolatile memory integrated circuit die, or with other unused pins of the device package. One or more additional external contacts may be added exclusively for the authentication integrated circuit die. One or more signals may be dedicated as between the standard nonvolatile memory IC die and the authentication IC die.

Abstract: A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“IC”) die, and the other being any suitable authentication IC die. Either die may be stacked upon the other, or the die may be placed side-by-side. The external contacts may correspond to the power and signal requirements of the standard nonvolatile memory IC die so that the pin-out of the memory device package may present a standard pinout. The power and signal requirements of the authentication IC die may be satisfied with some or all of the pins for the nonvolatile memory integrated circuit die, or with other unused pins of the device package. One or more additional external contacts may be added exclusively for the authentication integrated circuit die. One or more signals may be dedicated as between the standard nonvolatile memory IC die and the authentication IC die.