Patents by Inventor Ming-Jen Liang

Ming-Jen Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145372
    Abstract: The present invention provides a decoding method, a memory controlling circuit unit, and a memory storage device. The decoding method includes: receiving a plurality of commands; reading a first physical programming unit to obtain a plurality of first data respectively by using a plurality of first reading voltage groups of a plurality of reading voltage groups based on a first read command of the plurality of commands and executing a first decoding operation in each of the plurality of first data, wherein a number of the plurality of first reading voltage groups is less than a number of the plurality of reading voltage groups; and executing other commands being different from the first read command of the plurality of commands when unsuccessfully executing the first decoding operation for each of the plurality of first data.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 12, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Publication number: 20200219567
    Abstract: The present invention provides a decoding method, a memory controlling circuit unit, and a memory storage device. The decoding method includes: receiving a plurality of commands; reading a first physical programming unit to obtain a plurality of first data respectively by using a plurality of first reading voltage groups of a plurality of reading voltage groups based on a first read command of the plurality of commands and executing a first decoding operation in each of the plurality of first data, wherein a number of the plurality of first reading voltage groups is less than a number of the plurality of reading voltage groups; and executing other commands being different from the first read command of the plurality of commands when unsuccessfully executing the first decoding operation for each of the plurality of first data.
    Type: Application
    Filed: February 25, 2019
    Publication date: July 9, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Publication number: 20200218647
    Abstract: A memory control method for a rewritable non-volatile memory module which includes a plurality of physical groups is provided according to an exemplary embodiment of the disclosure. The memory control method includes: storing first table information into a first physical group among the physical groups, wherein the first table information records management information corresponding to a first logical range; storing second table information into a second physical group among the physical groups, wherein the second table information also records the management information corresponding to the first logical range; and instructing a reading of the second table information from the second physical group to obtain the management information corresponding to the first logical range in response to that the first physical group is in a default status.
    Type: Application
    Filed: February 20, 2019
    Publication date: July 9, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Patent number: 9996415
    Abstract: A data correcting method for a rewritable non-volatile memory module is provided. The method includes: if a first user data read from a first physical programming unit cannot be corrected by a corresponding first parity code, reading at least one group parity code of a first encoded group that the first physical programming unit belongs to into a buffer, sending the group parity code to a correcting circuit, and reading a user data from physical programming units belonging to the first encoded group into the buffer and sending the user data and the group parity code to the correcting circuit in batches to obtain a corrected first user data corresponding to the first user data.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: June 12, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Jen Liang, Kheng-Chong Tan
  • Publication number: 20170300379
    Abstract: A data correcting method for a rewritable non-volatile memory module is provided. The method includes: if a first user data read from a first physical programming unit cannot be corrected by a corresponding first parity code, reading at least one group parity code of a first encoded group that the first physical programming unit belongs to into a buffer, sending the group parity code to a correcting circuit, and reading a user data from physical programming units belonging to the first encoded group into the buffer and sending the user data and the group parity code to the correcting circuit in batches to obtain a corrected first user data corresponding to the first user data.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 19, 2017
    Inventors: Ming-Jen Liang, Kheng-Chong Tan
  • Patent number: 9665480
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The memory management method includes: grouping a plurality of non-spare physical erasing units into a first physical erasing unit and a second physical erasing unit, and a data updating frequency of the first physical erasing unit is lower than the data updating frequency of the second physical erasing unit; selecting a third physical erasing unit from the physical erasing units belonging to the first physical erasing unit; selecting a fourth physical erasing unit from spare physical erasing units, and copying valid data stored in the third physical erasing unit to the fourth physical erasing unit.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: May 30, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Patent number: 9448868
    Abstract: A data storing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes recording a bit error count of every predetermined area of every physical erasing unit and determining whether the bit error count of one of the predetermined areas of the physical programming unit of the physical erasing unit is more than a threshold bit error count. If the bit error count of one of the predetermined areas of the physical programming unit of the physical erasing unit is more than the threshold bit error count, the method also includes storing data under a second programming mode after an erasing operation is performed on the physical easing unit. Accordingly, defective physical erasing units may be effectively employed to prolong the lifespan of the memory storage apparatus.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: September 20, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Patent number: 9430325
    Abstract: A method for programming data, a memory storage device and a memory control circuit unit are provided. The method includes: receiving a writing command which instructs to write data to a logical address belonging to a logical programming unit; if a physical erasing unit of a physical programming unit which the logical programming unit is mapped to is a first type physical erasing unit, programming the data and a parity code corresponding to the data into the physical programming unit according to a first code rate; and if the physical erasing unit is a second type physical erasing unit, programming the data and the parity code corresponding to the data into the physical programming unit according to a second code rate. The first code rate is higher than the second code rate. Therefore, the lifespan of the physical erasing unit having a higher bit error rate may be extended.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: August 30, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Patent number: 9298610
    Abstract: A data writing method, and a memory control circuit unit and a memory storage apparatus using the method are provided. The method includes: grouping the logical units into a first area and at least a second area according to the write counts of the logical units configured on the memory apparatus. The method also includes: determining whether the logical unit corresponding to the received data belongs to the first area. The method further includes: if the logical unit corresponding to the received data belongs to the first area, programming the received data into a first active physical erasing unit, and if the logical unit corresponding to the received data belongs to the first area, programming the received data into a second active physical erasing unit. Accordingly, the method may improve the efficiency of a garbage collection operation.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 29, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Patent number: 9280460
    Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units, and a memory control circuit unit and the memory storage apparatus are provided. The method includes grouping the physical erasing units into at least a data area, a backup area and a spare area; and setting a value obtained by summing a minimum threshold and a predetermined number as a garbage collecting threshold. The data writing method also includes getting at least one physical erasing unit from the spare area, writing data into the gotten physical erasing unit, associating the gotten physical erasing unit with the backup area and re-adjusting the garbage collecting threshold according to the number of physical erasing units associated with the backup area and the minimum threshold.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: March 8, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Patent number: 9268687
    Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units, and a memory control circuit unit and the memory storage apparatus are provided. The method includes: grouping the physical erasing units into at least a data area and a spare area; configuring a plurality of logical units for mapping to the physical erasing units of the data area; and dynamically reserving a predetermined number of physical erasing units dedicating to write sequential data. Accordingly, the method can fast write the sequential data with the page-based memory management.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: February 23, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Patent number: 9208021
    Abstract: A data writing method, a memory storage device, and a memory controller for controlling a rewritable non-volatile memory module are provided. The rewritable non-volatile memory module includes at least one memory chip, and each memory chip includes a plurality of physical erasing units. The data writing method includes following steps. A data is written into at least one first physical erasing unit. A first error correction code and a second error correction code are respectively generated according to the data, where a number of bits correctable to the second error correction code is greater than a number of bits correctable to the first error correction code. The second error correction code is written into a second physical erasing unit. The first physical erasing unit and the second physical erasing unit belong to the same memory chip. Thereby, the memory space can be efficiently used.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: December 8, 2015
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Patent number: 9201785
    Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes receiving a write command and data corresponding to the write command from a host system and temporarily storing the data into a buffer memory, and the data includes a plurality of sub-data streams. The method still includes transmitting the sub-data streams into the rewritable non-volatile memory module, thereby writing the sub-data streams into at least one physical erasing unit of the rewritable non-volatile memory module. The method further includes generating parity information based on at least portion of the sub-data streams; storing the parity information into the buffer memory and deleting the data from the buffer memory. Accordingly, the method can effectively utilize the storage space of the buffer memory.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: December 1, 2015
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Kheng-Chong Tan, Ming-Jen Liang
  • Publication number: 20150339225
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The memory management method includes: grouping a plurality of non-spare physical erasing units into a first physical erasing unit and a second physical erasing unit, and a data updating frequency of the first physical erasing unit is lower than the data updating frequency of the second physical erasing unit; selecting a third physical erasing unit from the physical erasing units belonging to the first physical erasing unit; selecting a fourth physical erasing unit from spare physical erasing units, and copying valid data stored in the third physical erasing unit to the fourth physical erasing unit.
    Type: Application
    Filed: July 11, 2014
    Publication date: November 26, 2015
    Inventor: Ming-Jen Liang
  • Publication number: 20150293814
    Abstract: A method for programming data, a memory storage device and a memory control circuit unit are provided. The method includes: receiving a writing command which instructs to write data to a logical address belonging to a logical programming unit; if a physical erasing unit of a physical programming unit which the logical programming unit is mapped to is a first type physical erasing unit, programming the data and a parity code corresponding to the data into the physical programming unit according to a first code rate; and if the physical erasing unit is a second type physical erasing unit, programming the data and the parity code corresponding to the data into the physical programming unit according to a second code rate. The first code rate is higher than the second code rate. Therefore, the lifespan of the physical erasing unit having a higher bit error rate may be extended.
    Type: Application
    Filed: June 12, 2014
    Publication date: October 15, 2015
    Inventor: Ming-Jen Liang
  • Publication number: 20150293809
    Abstract: A data storing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes recording a bit error count of every predetermined area of every physical erasing unit and determining whether the bit error count of one of the predetermined areas of the physical programming unit of the physical erasing unit is more than a threshold bit error count. If the bit error count of one of the predetermined areas of the physical programming unit of the physical erasing unit is more than the threshold bit error count, the method also includes storing data under a second programming mode after an erasing operation is performed on the physical easing unit. Accordingly, defective physical erasing units may be effectively employed to prolong the lifespan of the memory storage apparatus.
    Type: Application
    Filed: June 6, 2014
    Publication date: October 15, 2015
    Inventor: Ming-Jen Liang
  • Publication number: 20150277785
    Abstract: A data writing method, and a memory control circuit unit and a memory storage apparatus using the method are provided. The method includes: grouping the logical units into a first area and at least a second area according to the write counts of the logical units configured on the memory apparatus. The method also includes: determining whether the logical unit corresponding to the received data belongs to the first area. The method further includes: if the logical unit corresponding to the received data belongs to the first area, programming the received data into a first active physical erasing unit, and if the logical unit corresponding to the received data belongs to the first area, programming the received data into a second active physical erasing unit. Accordingly, the method may improve the efficiency of a garbage collection operation.
    Type: Application
    Filed: May 30, 2014
    Publication date: October 1, 2015
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Patent number: 9122498
    Abstract: A firmware code loading method for loading a firmware code from a rewritable non-volatile memory module of a memory storage apparatus is provided. The method includes: obtaining a storage address for storing a first portion firmware code copy corresponding to a first portion of the firmware code in a first memory part; and obtaining a storage address for storing a second portion firmware code copy corresponding to a second portion of the firmware code in a second memory part. The method further includes: using a parallel mode or a interleave mode to load the first portion firmware code copy and the second portion firmware code copy respectively from the first memory part and the second memory part into a buffer memory. Accordingly, the method can effectively shorten the time of loading the firmware code.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: September 1, 2015
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Publication number: 20150193340
    Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units, and a memory control circuit unit and the memory storage apparatus are provided. The method includes grouping the physical erasing units into at least a data area, a backup area and a spare area; and setting a value obtained by summing a minimum threshold and a predetermined number as a garbage collecting threshold. The data writing method also includes getting at least one physical erasing unit from the spare area, writing data into the gotten physical erasing unit, associating the gotten physical erasing unit with the backup area and re-adjusting the garbage collecting threshold according to the number of physical erasing units associated with the backup area and the minimum threshold.
    Type: Application
    Filed: March 26, 2014
    Publication date: July 9, 2015
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Patent number: 9063888
    Abstract: A method of loading a program code from a rewritable non-volatile memory module is provided, wherein the program code includes data segments and two program code copies corresponding to the program code are stored in the rewritable non-volatile memory module. The method includes loading a first data segment of a first program code copy and determining whether the first data segment contains any uncorrectable error bit. The method still includes, when the first data segment does not contain any uncorrectable error bit, loading a second data segment of the first program code copy. The method further includes, when the first data segment contains an uncorrectable error bit, loading a first data segment of a second program code copy, and then loading a second data segment of the first program code copy or the second program code copy. Thereby, the program code can be successfully loaded.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: June 23, 2015
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang