Abstract: A manufacturing method of a thin film transistor (TFT) having low serial impedance is described. The method uses a back-side exposure and uses the active area as a hard mask; therefore, photomask usage may be reduced. On the other hand, a Si-Ge layer is used to react with the conductive layer deposited thereon after for forming a Ge-salicide layer. The method may reduce the required temperature of forming a Ge-salicide layer and the serial impedance.

Abstract: The present invention provides processes useful in the preparation of certain &bgr;3-adrenergic receptor agonists of the structural formula 1

Abstract: A manufacturing method of a thin film transistor (TFT) having low serial impedance is described. The method uses a back-side exposure and uses the active area as a hard mask; therefore, photomask usage may be reduced. On the other hand, a Si—Ge layer is used to react with the conductive layer deposited thereon after for forming a Ge-salicide layer. The method may reduce the required temperature of forming a Ge-salicide layer and the serial impedance.

Abstract: A system that can be dynamically configured to achieve an optimal routing path for an end-to-end data link connection is disclosed. An optimal data path can be determined by a digital subscriber loop (DSL) user based on particular bandwidth requirements, data rate cost constraints, and/or data delay requirements. The data path can be set up to include one or more data routes, including the regular digital public switching telephone network (PSN), a wide area networks (WAN), or virtual permanent circuit links via digital cross-connects (DCS).

Abstract: An analog front end (AFE) circuit used in a high-speed communications system is presented that includes multiple stages each including a bandpass filter, base band modulator, low pass filter and Sigma-Delta modulator. Each stage processes a fractional portion of the total frequency of a wide bandwidth analog signal. The number of such AFE stages is configurable in parallel to process the entire bandwidth of the received signal. The AFEs can be incorporated in a single integrated circuit or similar suitable manner so as to be modular, and easily replaceable/upgradeable. To achieve minimum quantization noise and reduce manufacturing costs, the Sigma-Delta modulators in each AFE are made to have identical characteristics. Because the wideband signal is broken down into smaller frequency portions, the sampling rate, and thus the complexity and cost associated with the AFEs, is reduced significantly.

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.

Abstract: A device or interface driver is provided for permitting an operating system to utilize, configure and control a software modem having forward compatible and expandable functionality. In a preferred embodiment, the operating system is a Windows based system running on a host processing system such as a personal computer, and the modem is compatible with standards promulgated for ADSL. Conventional voice band modem control commands are also supported, so that the present invention for ADSL based modems is nevertheless compatible with existing modem applications programs. The new driver manages control information for configuring the bandwidth to be used in a data link established through a channel with an upstream transciever during an initialization process, and serves as a data pump for the software modem. The control information may be self-determined by a user of the host processing system 398, or alternatively, automatically sensed, configured and monitored by such processing system.

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.

Abstract: A physical medium dependent (PMD) transport subsystem is disclosed which is used in an xDSL communication system. The PMD subsystem coordinates movement of data from an analog front end to a logical pipeline based TC layer, and exchanges common data objects with the latter to increase flexibility of the system. The PMD subsystem includes a number of ASIC blocks for performing signal processing operations, and these ASIC blocks are also shared between ports and are multi-tasking to reduce hardware costs.

Abstract: A system that can be dynamically configured to achieve an optimal routing path for an end-to-end data link connection is disclosed. An optimal data path can be determined by a digital subscriber loop (DSL) user based on particular bandwidth requirements, data rate cost constraints, and/or data delay requirements. The data path can be set up to include one or more data routes, including the regular digital public switching telephone network (PSTN), a wide area networks (WAN), or virtual permanent circuit links via digital cross-connects (DCS).

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.

Abstract: A multi-port communications system is described, which includes hardware based subsystems for performing both physical medium dependent operations and transport convergence operations on a data transmission. A software based subsystem performs other operations as needed. Both types of subsystems are shareable by the communications ports so as to reduce a total hardware requirement of a communications system. In addition, processing blocks within both subsystems are adapted to be multi-tasking, in that they can perform multiple operations for a receive/transmit task, or even a mixture of receive/transmit tasks. The subsystems are arrangeable in a logical/hybrid pipeline arrangement with a common memory to further maximize the flexibilty and configurability of a communications system.

Abstract: A structure for a data object is disclosed with a field and format structure optimized for use by a set of pipeline stages that are interconnected logically through a common pipeline memory. The data object includes both a first portion containing data relating to one or more of a plurality of parameters associated with the control and/or the configuration of one or more processing circuitry blocks, and a second portion containing data associated with computations performed by the processing circuitry blocks. Other portions contain both general and specific types of operational control information used by the processing circuitry blocks. The data object acts as a form of common data exchange mechanism between disparate types of pipeline stages, including in hybrid (mixed) software-hardware pipelines. The control data in the data object can be used by a first pipeline stage to affect or adaptively change operational functioning of downstream pipeline stages.

Abstract: An improved type of application-specific integrated circuit block (ASIC) is disclosed that is optimized for use in a communications system, and is somewhat programmble through the use of particular data objects that can specify an instruction and operand for the ASIC. The ASIC can be multi-tasking to perform multiple receive or transmit operations, two different kinds of transmit or receive operations, and operaions for mulitple ports. The ASIC generally uses an input data decoder block for decoding an input data object; a computation logic block for performing application specific computations in connection with the input data object, and an output data encoder block for encoding an output data object based on the specific computations. Using a common memory, a set of such ASICs can be arranged in a form of logical (or logical hybrid) pipeline.

Abstract: A logical pipeline or logical hybrid pipeline is used for an xDSL communication system, and particularly for processing DMT symbols. This flexible arrangement permits easy and efficient sequencing of DMT symbols for transmit/receive tasks, and for multiple ports, since the pipeline resources can be shared or allocated as needed to support a particular data transmission. Each stage in the pipelines works on input data objects, and creates output data objects in the same format for use by other stages. The data objects are based on DMT symbols, so this facilitates intelligent control and sequencing of a DMT data transmission. The combination of the pipeline and the tailored data objects permits an implementation of a customized xDSL symbol processor.

Abstract: A task scheduler for a TC subsystem is disclosed. The task scheduler is responsible for responding to computation block requests from the TC subsystem, and retrieving/storing data objects for such computation blocks. The task scheduler thus facilitates a type of logical pipeline by exchanging such data objects with a common TC memory used by each computation block. The task scheduler generally includes a queue, a state machine and a bus master for satisfying the data object requests.

Abstract: A transport convergence (TC) subsystem for use as a form of logical pipeline processor is disclosed. The TC subsystem includes a number of ASIC computing blocks interconnected through a local bus for transferring data objects used as a form of common data I/O for each ASIC. The data object includes both control and data portions. A TC scheduling circuit coordinates transfer of data objecst to and from a TC data object memory that is local or external. The TC data object memory is shared in common with all the ASIC blocks so that computation results from each ASIC TC signal processing circuit can be passed between other ASICs to form a logical pipeline. The data objects output from the TC subsystem are used by other processing subsystems in an XDSL communications system, including a software based ATM TC subsystem, and a physical medium dependent subsystem. In addition, the architecture of the TC subsystem is configured so that it can be shared by multiple ports in an xDSL system.

Abstract: A communications system includes a shared signal processing circuit for performing a set of signal processing operations on both receive data and said transmit data. The signal processing circuit is also shared by a plurality of communications ports. To further enhance operation of the system, the computing resources include a set of independent application specific (ASIC) logic circuits, with at least some of the ASICs selectively performing either a first signal processing operation and/or a second signal processing operation on data in response to control information embedded in an input data object.

Abstract: A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs acheivable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field.