Abstract: An electronic apparatus including a substrate, a baseband component and an electronic assembly is disclosed. The substrate has a first surface and a second surface opposite to the first surface. The baseband component is disposed on the first surface and electrically connected to the substrate. The electronic assembly includes an integrated passive device and a radio frequency component. The integrated passive device is disposed on the second surface and electrically connected to the substrate. The radio frequency component is disposed on the integrated passive device and electrically connected to the integrated passive device.

Abstract: A power amplifier amplifying an input signal to generate an output signal, comprising a cascode unit and a bias circuit. The cascode unit comprises a cascode stage, a first input stage, and a second input stage. The cascode stage generates the output signal. The first input stage, in cascode with the cascode transistor, has a first signal input to be biased to provide a first amplifier gain. The second input stage, in cascode with the cascode transistor, has a second signal input to be biased to provide a second amplifier gain. The bias circuit, coupled to the first and the second input stages comprises first and second switches. The first switch, coupled to the first input stage, is switched on to bias the first input stage with a bias voltage. The second switch, coupled to the second input stage, is switched on to bias the second input stage with the bias voltage.

Abstract: A layout structure of electrostatic discharge (ESD) protection circuit cooperated with an ESD protection device includes a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is disposed on the ESD protection device and electrically connected to the ESD protection device. The second electrically conductive layer is disposed on the first electrically conductive layer and electrically connected to the first electrically conductive layer. A width or a projection area of the second electrically conductive layer is less than that of the first electrically conductive layer.

Abstract: A selective etching method with lateral protection function is provided. The steps includes: (a) providing a substrate; (b) forming a plurality of tunnels; (c) forming a lateral strengthening structure at a peripheral wall of the tunnels; (d) removing a bottom portion of the lateral strengthening structure, and a part of the substrate by an etching process so as to form a lower structure and expose an unstrengthened structure; and (f) etching the unstrengthened structure laterally so as to form an upper structure.

Abstract: A high-aspect-ratio-microstructure (HARM) is provided. The structure includes: a substrate; a lower structure with a comb shape fixedly mounted on said substrate and having first plural comb fingers, wherein each of the first plural comb fingers has a thin slot thereon; an upper structure with a comb shape having second plural comb fingers, wherein the lower structure and the upper structure have a height difference therebetween so as to form an uneven surface; and a lateral strengthening structure formed at vertically peripheral walls of the first plural comb fingers and the second plural comb fingers for protecting the plural first and second comb fingers.

Abstract: A high-aspect-ratio-microstructure (HARM) is provided. The structure includes: a substrate; a lower structure with a comb shape fixedly mounted on said substrate and having first plural comb fingers, wherein each of the first plural comb fingers has a thin slot thereon; an upper structure with a comb shape having second plural comb fingers, wherein the lower structure and the upper structure have a height difference therebetween so as to form an uneven surface; and a lateral strengthening structure formed at vertically peripheral walls of the first plural comb fingers and the second plural comb fingers for protecting the plural first and second comb fingers.

Abstract: A selective etching method with lateral protection function is provided. The steps includes: (a) providing a substrate; (b) forming a plurality of tunnels; (c) forming a lateral strengthening structure at a peripheral wall of the tunnels; (d) removing a bottom portion of the lateral strengthening structure, and a part of the substrate by an etching process so as to form a lower structure and expose an unstrengthened structure; and (f) etching the unstrengthened structure laterally so as to form an upper structure.

Abstract: The present invention provides a fingerprint sensing mechanism using a two-dimensional thermoelectric sensor array to capture the thermal image related to the ridges and valleys on the finger, wherein its fabricating method is totally compatible with integrated circuits processing. Using the body temperature of a human being as the stimulation source for biometrics, a temperature difference is produced from a ridge of a fingerprint contacting the thermoelectric sensor and the temperature gradient is converted into an electrical signal. A plurality of thermoelectric sensors arranged in a two-dimensional array forms a fingerprint sensor so as to obtain the electrical signal output of the ridge profile of the fingerprint.

Abstract: A method for manufacturing a bidirectionally vertical motion actuator includes the steps of: providing a silicon-on-insulator (SOI) wafer, which comprises a first silicon wafer, an insulation layer on a top surface of the first silicon wafer, and a second silicon wafer; forming a dielectric layer on the SOI wafer by way of deposition; depositing a conductive layer on the dielectric layer; etching the conductive layer, the dielectric layer and the second silicon wafer simultaneously to form a proper top trench; and forming an anisotropic etching groove on a backside of the SOI wafer. A bidirectionally vertical motion actuator formed using the method is also disclosed.