Patents by Inventor Ming Liu

Ming Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11719880
    Abstract: A perovskite optical element includes a light guiding unit and a luminescent layer. The light guiding unit is configured to conduct light and serves as a resonant cavity. The luminescent layer is a thin film made of perovskite material and clads the light guiding unit. The luminescent layer is configured to be excited by an excitation module to emit light. The light is conducted and output by the light guiding unit. A manufacturing method of a perovskite optical element includes preparing a dip coating solution; dipping a single crystal optical fiber in the dip coating solution for one hour, removing the single crystal optical fiber out of the dip coating solution, and drying the single crystal optical fiber; and placing the single crystal optical fiber into a tube furnace, heating the crystal optical fiber, and introducing synthetic molecules into the tube furnace.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: August 8, 2023
    Assignee: NATIONAL DONG HWA UNIVERSITY
    Inventors: Duc-Huy Nguyen, Jia-Yuan Sun, Chia-Yao Lo, Jia-Ming Liu, Wan-Shao Tsai, Ming-Hung Li, Sin-Jhang Yang, Cheng-Chia Lin, Shien-Der Tzeng, Yuan-Ron Ma, Ming-Yi Lin, Chien-Chih Lai
  • Patent number: 11723135
    Abstract: An intelligent lighting device controller includes a detecting module, a main power source module and an intelligent control module. The detecting module has a detecting circuit. The main power source module has a plurality of first electrode connectors and a common second electrode connector. The first electrode connectors are connected to the detecting circuit and connected to the first electrodes of a plurality of lighting devices respectively via the detecting circuit. The common second electrode connector outputs an electricity signal to drive the lighting devices. The intelligent control module is connected to the detecting module and the main power source module. The detecting circuit generates a plurality of detecting signals corresponding to the lighting devices respectively. The intelligent control module generates a feedback signal and transmits the feedback signal to the main power source module. The main power source module adjusts the electricity signal according to the feedback signal.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: August 8, 2023
    Assignee: Xiamen PVTECH Co., Ltd.
    Inventors: Fuxing Lu, Rongtu Liu, Chun Ming Liu
  • Patent number: 11722423
    Abstract: Disclosed is a data flow classification device including a forwarding circuit and a configuring circuit. The forwarding circuit looks the classification of an input flow up in a lookup table according to the information of the input flow, tags the packets of the input flow with the classification, and outputs the packets to a buffer circuit. The configuring circuit receives and stores the identification and traffic information of multiple flows, and accordingly calculates the traffic of the multiple flows, wherein the multiple flows include the input flow. The configuring circuit further determines an elephant flow threshold according to a queue length of the buffer circuit and a target length, determines the classifications of the multiple flows according to the comparison between the traffic of the multiple flows and the elephant flow threshold, and stores these classifications in the lookup table.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: August 8, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuo-Cheng Lu, Min-Chang Wei, Chun-Ming Liu, Kuang-Yu Yen
  • Patent number: 11717803
    Abstract: Porous materials (such as organic polyamine cage compounds) and methods of stabilising porous materials which are otherwise prone to pore-collapse are described. Such stabilisation is accomplished through the use of molecular ties to create bridges between reactive groups of a (potentially) porous material to thereby strengthen and stabilise the porous structure. The chemistry involved in, and the results of, the stabilisation of porous materials to provide a new sorption composition comprising the very materials which are generally prone to pore-collapse are also described.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: August 8, 2023
    Inventors: Andy Cooper, Ming Liu
  • Patent number: 11721597
    Abstract: A semiconductor device and a method for detecting a defect in a semiconductor device are provided. The semiconductor device includes a packaging structure. The packaging structure includes a redistribution layer and a detecting component disposed in the redistribution layer. The semiconductor device further includes a cooling plate over the packaging structure and a fixing component penetrating through the packaging structure and the cooling plate. The packaging structure and the cooling plate are fixed by the fixing component. The detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu
  • Publication number: 20230245691
    Abstract: Provided is a cache memory, including: a first field-effect transistor, a field-like spin torque layer underneath a magnetic tunnel junction, an electrode, and a second field-effect transistor sequentially arranged and connected; wherein the first field-effect transistor is configured to provide a writing current and to control the on-off of the writing current through a gate electrode; the field-like spin torque layer is configured to generate field-like spin torques for switching a first ferromagnetic layer of the magnetic tunnel junction; the magnetic tunnel junction includes a first ferromagnetic layer, a tunneling layer, a second ferromagnetic layer and a pinning layer arranged sequentially; the electrode is configured to connect the cache memory with the second field-effect transistor; and the second field-effect transistor is configured to control the on-off of the second field-effect transistor through the gate electrode to read the resistive state of the magnetic tunnel junction.
    Type: Application
    Filed: July 20, 2020
    Publication date: August 3, 2023
    Inventors: Chong BI, Ming LIU
  • Patent number: 11709999
    Abstract: The present application discloses a method and apparatus for acquiring point-of-interest (POI) state information, a device and a computer storage medium, and relates to the field of big data. An implementation includes acquiring a text containing POI information in a preset time period from the Internet; and identifying the text using a pre-trained POI-state identifying model to obtain a binary group in the text, the binary group including a POI name and the POI state information corresponding to the POI name; wherein the POI-state identifying model performs label prediction of the POI name and a POI state on a word sequence corresponding to the text, and label prediction results of the POI name and the POI state are aligned to obtain the binary group. With the present application, a human cost may be saved, and timeliness and accuracy may be improved.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: July 25, 2023
    Assignee: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) CO., LTD.
    Inventors: Jizhou Huang, Yibo Sun, Ying Li, Ming Liu, Bing Qin
  • Publication number: 20230232537
    Abstract: A package circuit structure includes a multilayer circuit board, an electronic component, and an insulating layer. The multilayer circuit board includes a metal portion and an opening. The opening is extending from a first side of the multilayer circuit board toward the second side of the multilayer circuit board facing the first side. A bottom of the opening is sealed by the metal portion. The electronic component is received in the opening and adhered to the metal portion. The electronic component is electrically connected to the multilayer circuit board and encapsulated in the opening by the insulating layer. A method for manufacturing the package circuit structure is also provided.
    Type: Application
    Filed: March 20, 2023
    Publication date: July 20, 2023
    Inventors: CHUN-CHIEH HUANG, CHIN-MING LIU
  • Publication number: 20230228195
    Abstract: A cycle residual boost and two release cavities are provided on a cylinder wall. Wankel cycle air pump is provided with additional cavities which allow the pressure output higher than its fixed compression ratio and further increase compression efficiency. An apex seal active tracking mechanism is also provided. Wankel cycle air pump rotor plates passage makes apex seals keep firmly contact against a cylinder.
    Type: Application
    Filed: March 20, 2023
    Publication date: July 20, 2023
    Inventors: Hung-Chih Huang, Huang-Ming Liu
  • Publication number: 20230232582
    Abstract: A server computer system has one or more node assemblies. A node assembly has two motherboards that are stacked one over another with their component sides facing toward each other. Memory cards that are mounted on one motherboard are interlaced with memory cards that are mounted on the other motherboard. At least processors of the two motherboards are immersed in a coolant fluid in a fluid immersion cooling tank. A processor cooling stack is mounted over a processor. The processor cooling stack includes flow regulation structures with sidewalls that regulate flow of vapor bubbles of the coolant fluid away from the processor.
    Type: Application
    Filed: January 20, 2022
    Publication date: July 20, 2023
    Applicant: Super Micro Computer, Inc.
    Inventors: Yueh Ming LIU, Yu Hsiang HUANG, Yu Chuan CHANG, Hsiao Chung CHEN, Tan Hsin CHANG
  • Patent number: 11705489
    Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 18, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, Manhsuan Lin
  • Patent number: 11702362
    Abstract: Technical fields of building external wall decoration and material manufacturing, providing a mildewproof and antirot high-strength cement particle board and a preparation method thereof. The preparation method includes: (1) sequentially carbonizing and water-washing a shaving, and mixing the obtained carbonized shaving with a cement gelling agent, a curing agent aqueous solution and water to obtain a mixture; (2) molding the mixture to obtain a pre-molded material; and (3) sequentially curing and drying the pre-molded material to obtain the mildewproof and antirot high-strength cement particle board. Compared to ordinary cement particle board, which is not subjected to carbonization treatment and water-washing, the cement particle board of the present invention can effectively avoid mildew and rot, and can significantly improve the mechanical strength and durability thereof, helping to extend the service life of the cement particle board.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: July 18, 2023
    Assignee: CENTRAL SOUTH UNIVERSITY OF FORESTRY AND TECHNOLOGY
    Inventors: Yiqiang Wu, Xingong Li, Xia Zheng, Yan Qing, Xianjun Li, Yingfeng Zuo, Ming Liu
  • Publication number: 20230215924
    Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.
    Type: Application
    Filed: March 9, 2023
    Publication date: July 6, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, Manhsuan Lin
  • Publication number: 20230197152
    Abstract: Provided are a memory cell structure, a memory array structure, and a voltage biasing method. The memory cell structure includes: a substrate layer, a well layer and a transistor. The substrate layer is configured to support the memory cell structure; the well layer is embedded in the substrate layer, an upper surface of the well layer is flush with an upper surface of the substrate layer, and a transistor is arranged on the well layer. In the present disclosure, a deep well bias is performed on the memory cell structure, so that the well voltage of the memory cell may be individually biased to a specific voltage, and in combination with the redesigned memory cell array structure, the applied programming voltage mostly falls on the memory cell structure.
    Type: Application
    Filed: April 14, 2020
    Publication date: June 22, 2023
    Inventors: Hangbing LV, Jianguo YANG, Xiaoxin XU, Ming LIU
  • Patent number: 11679549
    Abstract: An additive manufacturing apparatus is disclosed including an additive manufacturing platform; a material feeding unit configured to feed a material onto the additive manufacturing platform; a laser generating unit configured to generate a laser beam with a linear light spot for projecting onto the material on the additive manufacturing platform; and a movement driving unit configured to drive at least one of the laser generating unit, the additive manufacturing platform and the material feeding unit to move in at least one direction. An additive manufacturing method is also disclosed. With the additive manufacturing apparatus and method, an additive manufacturing process can be performed efficiently, and are particularly suitable for an additive manufacturing process of large-size components.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: June 20, 2023
    Assignee: AIRBUS (BEIJING) ENGINEERING CENTRE COMPANY LIMITED
    Inventor: Ming Liu
  • Patent number: 11683888
    Abstract: A package circuit structure includes a multilayer circuit board, an electronic component, and an insulating layer. The multilayer circuit board includes a metal portion and an opening. The opening is extending from a first side of the multilayer circuit board toward the second side of the multilayer circuit board facing the first side. A bottom of the opening is sealed by the metal portion. The electronic component is received in the opening and adhered to the metal portion. The electronic component is electrically connected to the multilayer circuit board and encapsulated in the opening by the insulating layer. A method for manufacturing the package circuit structure is also provided.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: June 20, 2023
    Assignees: Leading Interconnect Semiconductor Technology Qinhuangdao Co, Ltd., Qi Ding Technology Qinhuangdao Co, Ltd., Leading Interconnect Semiconductor Technology (ShenZhen) Co, Ltd.
    Inventors: Chun-Chieh Huang, Chin-Ming Liu
  • Publication number: 20230185640
    Abstract: A method may include defining a rule identifying an event that triggers a change in a value of a metric. The defining of the rule includes generating a subscription to receive the event from an event stream. Occurrences of the event identified by the rule may be detected based on receiving the event from the event stream. In response to each occurrence of the event, the value of the metric and/or the change in the value of the metric may be evaluated. A notification may be sent to a software application consuming the metric based on the value of the metric and/or the change in the value of the metric satisfying a threshold. Related systems and computer program products are also provided.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: Tao Zhang, Daniel Intoppa, Ming Liu
  • Patent number: 11674137
    Abstract: Disclosed is an adaptor for sequencing DNAs at ultratrace levels and its uses. The adaptor contains, from 5?terminus to 3?terminus, a Tag sequence, PolyNs, a first stem sequencing, a first loop sequence, dUTP(s), a second loop sequence, and a second stem sequence, wherein the second stem sequence is complementary to the first stem sequence when read in opposite directions, and the 5?terminus of the adaptor is phosphorylated. The adaptor is designed to form a hairpin structure itself in use and then ligated to a DNA molecule of interest, so that adaptor-adaptor ligation can be effectively avoided, eliminating the inefficient adaptor-DNA ligation problem. Such an adaptor is especially suitable for library construction and sequencing of DNAs at ultratrace levels, laying a good basis for accurate sequencing of ctDNAs.
    Type: Grant
    Filed: May 27, 2017
    Date of Patent: June 13, 2023
    Inventors: Xiaoni Zhang, Ming Liu, Guolin Zhong, Mingyan Xu
  • Patent number: D989738
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: June 20, 2023
    Inventor: Ming Liu
  • Patent number: D989739
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: June 20, 2023
    Inventor: Ming Liu