Patents by Inventor Ming-Ren Lin
Ming-Ren Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105632Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
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Patent number: 8580660Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.Type: GrantFiled: June 14, 2012Date of Patent: November 12, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Ming-Ren Lin, Judy Xilin An, Zoran Krivokapic, Cyrus E. Tabery, Haihong Wang, Bin Yu
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Patent number: 8502283Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.Type: GrantFiled: October 29, 2007Date of Patent: August 6, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Qi Xiang, Niraj Subba, Witold P. Maszara, Zoran Krivokapic, Ming-Ren Lin
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Patent number: 8431466Abstract: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.Type: GrantFiled: July 5, 2011Date of Patent: April 30, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Ming-ren Lin, Zoran Krivokapic, Witek Maszara
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Publication number: 20120252193Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.Type: ApplicationFiled: June 14, 2012Publication date: October 4, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Ming-Ren LIN, Judy Xilin AN, Zoran KRIVOKAPIC, Cyrus E. TABERY, Haihong WANG, Bin YU
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Patent number: 8222680Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.Type: GrantFiled: October 22, 2002Date of Patent: July 17, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Ming-Ren Lin, Judy Xilin An, Zoran Krivokapic, Cyrus E. Tabery, Haihong Wang, Bin Yu
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Publication number: 20110263094Abstract: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.Type: ApplicationFiled: July 5, 2011Publication date: October 27, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Ming-ren LIN, Zoran KRIVOKAPIC, Witek MASZARA
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Patent number: 8008136Abstract: A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.Type: GrantFiled: April 20, 2006Date of Patent: August 30, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Ming-Ren Lin, Witold P. Maszara, Haihong Wang, Bin Yu
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Patent number: 7994020Abstract: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.Type: GrantFiled: July 21, 2008Date of Patent: August 9, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Ming-ren Lin, Zoran Krivokapic, Witek Maszara
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Patent number: 7871873Abstract: A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.Type: GrantFiled: March 27, 2009Date of Patent: January 18, 2011Assignee: GLOBAL FOUNDRIES Inc.Inventors: Witold Maszara, Ming-Ren Lin, Jin Cho, Zoran Krivokapic
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Publication number: 20100248454Abstract: A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.Type: ApplicationFiled: March 27, 2009Publication date: September 30, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Witold MASZARA, Ming-Ren LIN, Jin CHO, Zoran KRIVOKAPIC
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Patent number: 7713834Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.Type: GrantFiled: September 5, 2008Date of Patent: May 11, 2010Assignee: GlobalFoundries Inc.Inventors: Haihong Wang, Minh-Van Ngo, Qi Xiang, Paul R. Besser, Eric N. Paton, Ming-Ren Lin
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Patent number: 7701019Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.Type: GrantFiled: February 17, 2006Date of Patent: April 20, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Minh V. Ngo, Paul R. Besser, Ming Ren Lin, Haihong Wang
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Publication number: 20100015778Abstract: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.Type: ApplicationFiled: July 21, 2008Publication date: January 21, 2010Applicant: Advanced Micro Devices, Inc.Inventors: Ming-ren LIN, Zoran KRIVOKAPIC, Witek MASZARA
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Patent number: 7648886Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.Type: GrantFiled: January 14, 2003Date of Patent: January 19, 2010Assignee: Globalfoundries Inc.Inventors: Minh-Van Ngo, Qi Xiang, Paul R. Besser, Eric N. Paton, Ming-Ren Lin
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Patent number: 7541267Abstract: A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.Type: GrantFiled: June 20, 2007Date of Patent: June 2, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Shibly S. Ahmed, Ming-Ren Lin, Bin Yu
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Patent number: 7498225Abstract: A method for forming fin structures for a semiconductor device that includes a substrate and a dielectric layer formed on the substrate is provided. The method includes etching the dielectric layer to form a first structure, depositing an amorphous silicon layer over the first structure, and etching the amorphous silicon layer to form second and third fin structures adjacent first and second side surfaces of the first structure. The second and third fin structures may include amorphous silicon material. The method further includes depositing a metal layer on upper surfaces of the second and third fin structures, performing a metal-induced crystallization operation to convert the amorphous silicon material of the second and third fin structures to a crystalline silicon material, and removing the first structure.Type: GrantFiled: July 5, 2006Date of Patent: March 3, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Shibly S. Ahmed, Ming-Ren Lin, Bin Yu
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Publication number: 20090047770Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.Type: ApplicationFiled: September 5, 2008Publication date: February 19, 2009Inventors: Haihong Wang, Minh-Van Ngo, Qi Xiang, Paul R. Besser, Eric N. Paton, Ming-Ren Lin
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Patent number: 7422961Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.Type: GrantFiled: March 14, 2003Date of Patent: September 9, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Minh-Van Ngo, Qi Xiang, Paul R. Besser, Eric N. Paton, Ming-Ren Lin
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Patent number: 7416925Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.Type: GrantFiled: February 21, 2007Date of Patent: August 26, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Ming-Ren Lin, Bin Yu