Abstract: A semiconductor device includes a first gate stack and a second gate stack, each gate stack corresponding to a gate of a FET formed on the semiconductor device. The first gate stack includes a gate material formed from one of poly-silicon, poly-SiGe, and amorphous silicon. The gate material is implanted with a dopant of a first conductivity type at a first concentration. A metal silicide layer is formed over the doped gate material. The second gate stack includes a gate material formed from one of poly-silicon, poly-Si—Ge, and amorphous silicon. The gate material of the second gate stack is implanted with a dopant of a second conductivity type at a second concentration.

Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

Abstract: An integrated circuit is provided having an improved packing density due to an improved isolation structure between a plurality of devices on the substrate. An ultra shallow trench isolation structure is provided, typically having a trench depth just deeper than the doped regions of a transistor or other device placed thereon, but substantially shallower than the depth of a well associated with the transistor. A nitrogen ion implantation step is utilized to fabricate an implanted portion beneath the insulative portion, the implanted portion extending preferably below the depth of the well. Due to a shallower trench isolation structure, the structure may also be narrower, providing for improved packing density in a semiconductor device.

Abstract: STI (Shallow Trench Isolation) structures are fabricated such that leakage current is minimized through a field effect transistor fabricated between the STI structures. The shallow trench isolation structure include a pair of isolation trenches, with each isolation trench being etched through a semiconductor substrate. A first dielectric material fills the pair of isolation trenches and extends from the isolation trenches such that sidewalls of the first dielectric material filling the isolation trenches are exposed beyond the top of the semiconductor substrate. A second dielectric material is deposited on the sidewalls of the first dielectric material exposed beyond the top of the semiconductor substrate. The second dielectric material has a different etch rate in an acidic solution from the first dielectric material filling the isolation trenches.

Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-k gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

Abstract: A MOS transistor having a source and drain extension that are less than 40 nanometers in thickness to minimize the short channel effect. A gate includes a high-K dielectric spacer layer to create depletion regions in the substrate which form the drain and source extensions.

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV.

Abstract: A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process, such as an activation anneal or a salicidation anneal of the source and drain of the field effect transistor, using relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and a crystallization enhancing layer is deposited on the bottom wall of the gate opening.

Abstract: A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration.

Abstract: A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

Abstract: A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.

Abstract: Submicron-dimensioned metallization patterns are formed on a substrate surface by a photo-activated selective, anisotropic etching process, wherein selective portions of a metal layer are exposed to collimated UV passing through a pattern of submicron-sized openings in an overlying exposure mask. At least one photo-activatable etching material contained in a gas flowed through the space between the substrate surface and the mask selectively and anisotropically etches the exposed portions of the metal layer in thereby avoiding numerous masking and etching steps as in conventional photolithographic methodology. The inventive method is of particular utility in performing multi-level, in-laid, “back-end” metallization processing of high-density integrated circuit semiconductor devices.

Abstract: A method of forming a MOSFET device is provided. First lightly doped regions are formed, the first lightly doped regions including LDD extension regions of the device. Second very lightly doped regions are formed at least partially below the first lightly doped regions, respectively, the second very lightly doped regions having a dopant concentration less than the first lightly doped regions, and the second very lightly doped regions being implanted at a higher energy level than the first lightly doped regions.

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally annealed to drive dopants from the solid-phase impurity source into the source and drain regions. The dopants from the impurity source provide ultra-shallow source and drain extensions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract: A method of performing tilted implantation for pocket, halo and source/drain extensions in ULSI dense structures. The method overcomes the process limit, due to shadowing effects, in dense structures, of using large angle tilted implant techniques in ULSI circuits. A gate opening in an oxide layer is defined and partially filled by insertion of nitride spacers to define an actual gate window opening. The small angle tilted implant technique has the equivalent doping effect of large angle tilted implants, and circumvents the maximum angle limit (&thgr;MAX) that occurs in the large angle implant method. The small angle tilted implant technique also automatically provides self alignment of the pocket/halo/extension implant to the gate of the device.

Abstract: Low resistivity contacts are formed on source/drain regions and gate electrodes at a suitable thickness to reduce parasitic series resistances, thereby significantly reducing consumption of underlying silicon, while significantly reducing junction leakage. Embodiments include selectively depositing a metal layer, such as nickel, on the source/drain regions and on the gate electrode and ion implanting to form a barrier layer within the nickel layers which does not react with silicon or nickel silicide during subsequent solicitation. The barrier layer confines salicidation to the relatively thin underlayer layer of nickel, thereby minimizing consumption of underlying silicon while the unsilicidized overlying nickel on the barrier layer ensures low sheet resistivity.

Abstract: In one embodiment, the present invention relates to a method of forming a Silicon-on-Insulator substrate involving the steps of providing a monocrystalline silicon substrate; patterning a mask over the monocrystalline silicon substrate thereby exposing a portion of the monocrystalline silicon substrate; implanting a first dosage of oxygen atoms in the exposed portion of the monocrystalline silicon substrate; removing the mask from the monocrystalline silicon substrate; implanting a second dosage of oxygen atoms without using an implantation mask in the monocrystalline silicon substrate; and annealing the oxygen implanted monocrystalline silicon substrate to provide the Silicon-on-Insulator substrate.

Abstract: An integrated circuit and a method of forming an integrated circuit is described. The integrated circuit includes a silicon substrate, a dielectric stack formed on the silicon substrate, and conductive metal lines overlying the silicon substrate. A first layer of low-k dielectric material overlies the at least one conductive metal line, and a second layer of low-k dielectric material overlies the first layer of low-k dielectric material. The first layer of low-k dielectric material is electron beam (E-beam) cured and the second layer of low-k dielectric material is thermally cured.

Abstract: Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

Abstract: A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process, such as an activation anneal or a salicidation anneal of the source and drain of the field effect transistor, using relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and amorphous gate electrode material, such as amorphous silicon, is deposited to fill the gate opening after the layer of dielectric has been deposited.