Patents by Inventor Ming Tsai

Ming Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387316
    Abstract: A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin LIANG, Min-Chiang CHUANG, Chia-Cheng CHEN, Chun-Hung WU, Liang-Yin CHEN, Sung-Li WANG, Pinyen LIN, Kuan-Kan HU, Jhih-Rong HUANG, Szu-Hsian LEE, Tsun-Jen CHAN, Cheng-Wei LIAN, Po-Chin CHANG, Chuan-Hui SHEN, Lin-Yu HUANG, Yuting CHENG, Yan-Ming TSAI, Hong-Mao LEE
  • Publication number: 20230377994
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
  • Publication number: 20230369130
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • Publication number: 20230367943
    Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Chi-Ta Lu, Chi-Ming Tsai
  • Patent number: 11817528
    Abstract: A nitride-based light-emitting diode (LED) device includes an n-type nitride semiconductor layer, an active layer disposed on the n-type nitride semiconductor layer, a p-type nitride semiconductor layer disposed on the active layer, and a defect control unit disposed between the n-type nitride semiconductor layer and the active layer. The defect control unit includes first, second and third defect control layers that are sequentially disposed on the n-type nitride semiconductor layer, and that have different doping concentrations. The third defect control layer includes one of Al-containing ternary nitride, Al-containing quaternary nitride, and a combination thereof.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: November 14, 2023
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Yung-Ling Lan, Chan-Chan Ling, Chi-Ming Tsai
  • Patent number: 11817018
    Abstract: The present invention is a message updating system for an electronic label. The system comprises a message updating device, wherein a controller thereof controls a power-supply transmission unit and a message-update transmission unit to respectively transmit a charging signal and a message-updating to the electronic label for charging the electronic label and updating label information of the electronic label. A detection device picks up the label information to generate label content information, transmits the label content information to the controller to make the controller compare the label content information with update comparison information, and generates an alert message if the label content information is different from the update comparison information. The present can charge the electronic label that is mounted on an article and update label information simultaneously while the article is being transported.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: November 14, 2023
    Assignee: Netronix, Inc.
    Inventors: Fang Ming Tsai, Jun Sheng Lin
  • Patent number: 11810826
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • Publication number: 20230341765
    Abstract: A method includes: providing a first design layout including a plurality of cells; updating a first cell of the plurality of cells using optical proximity correction to provide a first updated cell and a data set; and updating a second cell from remaining cells in the first design layout based on the data set and a model without involvement of optical proximity correction to provide a second updated cell, wherein the model includes hidden layers including nodes and is trained to obtaining converged values of the nodes of the hidden layers through providing a mapping of edge segments before lithography enhancement and edge segments after lithography enhancement using optical proximity correction, and wherein at least one of the providing, and updating is executed by one or more processors.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: WEI-LIN CHU, HSIN-LUN TSENG, SHENG-WEN HUANG, CHIH-CHUNG HUANG, CHI-MING TSAI
  • Patent number: 11800102
    Abstract: Low-latency video coding methods and apparatuses include receiving input data associated with a current Intra slice composed of Coding Tree Units (CTU), where each CTU includes luma and chroma Coding Tree Blocks (CTBs), partitioning each CTB into non-overlapping pipeline units, and encoding or decoding the CTUs in the current Intra slices by performing processing of chroma pipeline units after beginning processing of luma pipeline units in at least one pipeline stage. Each of the pipeline units is processed by one pipeline stage after another pipeline stage, and different pipeline stages process different pipeline units simultaneously. The pipeline stage in the low-latency video coding methods and apparatuses simultaneously processes one luma pipeline unit and at least one previous chroma pipeline unit within one pipeline unit time interval.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: October 24, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chia-Ming Tsai, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11784187
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
  • Publication number: 20230314953
    Abstract: Embodiments described herein relate to methods of printing features within a lithography environment. The methods include determining a mask pattern. The mask pattern includes auxiliary features to be provided with main features to a maskless lithography device in a lithography process. The auxiliary features are determined with a rule-based process flow or a lithography model process flow.
    Type: Application
    Filed: September 16, 2021
    Publication date: October 5, 2023
    Inventors: Chi-Ming TSAI, Thomas L. LAIDIG, Douglas Joseph VAN DEN BROEKE, Jang Fung CHEN
  • Publication number: 20230318310
    Abstract: The present invention provides a control system in which an energy-saving brushless micro-kinetic energy generating device is connected in parallel with a mains power supply device. The control system detects the actual power consumption of the load end, so that the control system of the invention can drive the switch according to the power consumption of the load end. An energy-saving brushless micro-kinetic energy generator or a mains power supply device is selected for power supply, so that users can achieve the effect of energy saving.
    Type: Application
    Filed: September 13, 2022
    Publication date: October 5, 2023
    Inventors: Chih-Ming Tseng, Jui-Ming Tsai
  • Patent number: 11762416
    Abstract: A transparent laminated film, a display device, and a method for manufacturing a transparent laminated film are disclosed. The transparent laminated film includes a first film layer, a central film layer, and a second film layer which are sequentially stacked, each of a material of the first film layer and a material of the second film layer includes a thermoplastic plastic, and a material of the central film layer includes a thermosetting plastic.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: September 19, 2023
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Penghao Gu, Jiahao Zhang, Pao Ming Tsai
  • Patent number: 11763057
    Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ta Lu, Chi-Ming Tsai
  • Patent number: 11765365
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream determines a block boundary of the current block and sub-block boundaries inside the current block, wherein the current block is partitioned into a plurality of sub-blocks using sub-block mode prediction. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a current filtered-reconstructed block, wherein said applying the de-blocking process to the current block comprises applying the de-blocking process to the sub-block boundaries inside the current filtered-reconstructed block, and generates a filtered decoded picture including the current filtered-reconstructed block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: September 19, 2023
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Publication number: 20230288812
    Abstract: Embodiments described herein relate to methods of printing double exposure patterns in a lithography environment. The methods include determining a second exposure pattern to be exposed with a first exposure pattern in a lithography process. The second exposure pattern is determined with a rule-based process flow or a lithography model process flow.
    Type: Application
    Filed: September 9, 2021
    Publication date: September 14, 2023
    Inventor: Chi-Ming TSAI
  • Publication number: 20230282729
    Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a fist work-function layer over the gate dielectric layer. The work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.
    Type: Application
    Filed: May 9, 2022
    Publication date: September 7, 2023
    Inventors: Hsin-Yi Lee, Chun-Da Liao, Cheng-Lung Hung, Yan-Ming Tsai, Harry Chien, Huang-Lin Chao, Weng Chang, Chih-Wei Chang, Ming-Hsing Tsai, Chi On Chui
  • Patent number: 11749612
    Abstract: A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: September 5, 2023
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Shih-Ping Hsu, Hsien-Ming Tsai
  • Publication number: 20230272841
    Abstract: A transmission system of a decelerating mechanism includes a planetary gear unit including a sun gear being adjacent to the first surface and a planetary gear set and a holder including a carrier and several planetary shaft units rotatably disposed on the carrier. The carrier has a first surface and a second surface that face opposite directions. The planetary gear set has several first gears being adjacent to the first surface, respectively fitting around the planetary shaft units, and meshing with the sun gear, several second gears being adjacent to the second surface and being coaxially disposed with the first gears, and an internal gear ring meshing with the second gears. By respectively arranging the first gears and the second gears on two opposite sides of the carrier, mutual interference therebetween while turning could be avoided, and an overall volume of the transmission system could be reduced.
    Type: Application
    Filed: February 20, 2023
    Publication date: August 31, 2023
    Applicant: TIEN HSIN INDUSTRIES CO., LTD.
    Inventors: MING-LAN OU, TSUNG-MING TSAI, YU-NONG WU
  • Publication number: 20230273024
    Abstract: A microelectromechanical system (MEMS) gyroscope includes a driving mass and a driving circuit that operates to drive the driving mass in a mechanical oscillation at a resonant drive frequency. An oscillator generates a system clock that is independent of and asynchronous to the resonant drive frequency. A clock generator circuit outputs a first clock and a second clock that are derived from the system clock. The drive loop of the driving circuit including an analog-to-digital converter (ADC) circuit that is clocked by the first clock and a digital signal processing (DSP) circuit that is clocked by the second clock.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 31, 2023
    Applicant: STMicroelectronics, Inc.
    Inventors: Deyou FANG, Chao-Ming TSAI, Milad ALWARDI, Yamu HU, David MCCLURE