Patents by Inventor Ming-Tsong Wang
Ming-Tsong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096784Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.Type: ApplicationFiled: January 3, 2023Publication date: March 21, 2024Inventors: Meng-Hsien Lin, Hsing-Chih Lin, Ming-Tsong Wang, Min-Feng Kao, Kuan-Hua Lin, Jen-Cheng Liu, Dun-Nian Yaung, Ko Chun Liu
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Patent number: 11894410Abstract: Some embodiments relate an integrated circuit (IC) including a first substrate including a plurality of imaging devices. A second substrate is disposed under the first substrate and includes a plurality of logic devices. A first interconnect structure is disposed between the first substrate and the second substrate and electrically couples imaging devices within the first substrate to one another. A second interconnect structure is disposed between the first interconnect structure and the second substrate, and electrically couples logic devices within the second substrate to one another. A bond pad structure is coupled to a metal layer of the second interconnect structure and extends along inner sidewalls of both the first interconnect structure and the second interconnect structure. An oxide layer extends from above the first substrate to below a plurality of metal layers of the first interconnect structure, and lines inner sidewalls of the bond pad structure.Type: GrantFiled: February 1, 2022Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang, Shih Pei Chou
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Patent number: 11342373Abstract: A method for manufacturing an image sensing device includes forming an interconnection layer over a front surface of a semiconductor substrate. A trench is formed to extend from a back surface of the semiconductor substrate. An etch stop layer is formed along the trench. A buffer layer is formed over the etch stop layer. An etch process is performed for etching the buffer layer. The buffer layer and the etch stop layer include different materials.Type: GrantFiled: April 8, 2020Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chuang Wu, Ming-Tsong Wang, Feng-Chi Hung, Ching-Chun Wang, Jen-Cheng Liu, Dun-Nian Yaung
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Publication number: 20220157864Abstract: Some embodiments relate an integrated circuit (IC) including a first substrate including a plurality of imaging devices. A second substrate is disposed under the first substrate and includes a plurality of logic devices. A first interconnect structure is disposed between the first substrate and the second substrate and electrically couples imaging devices within the first substrate to one another. A second interconnect structure is disposed between the first interconnect structure and the second substrate, and electrically couples logic devices within the second substrate to one another. A bond pad structure is coupled to a metal layer of the second interconnect structure and extends along inner sidewalls of both the first interconnect structure and the second interconnect structure. An oxide layer extends from above the first substrate to below a plurality of metal layers of the first interconnect structure, and lines inner sidewalls of the bond pad structure.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang, Shih Pei Chou
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Patent number: 11244981Abstract: Some embodiments relate an integrated circuit (IC). The IC includes a first substrate including an array of photodetectors, wherein a bond pad opening extends through the first substrate and is defined by an inner sidewall of the first substrate. An interconnect structure is disposed over the first substrate and includes a plurality of metal layers stacked over one another and disposed within a dielectric structure. The bond pad opening further extends through at least a portion of the interconnect structure and is further defined by an inner sidewall of the interconnect structure. A bond pad structure directly contacts a metal layer of the plurality of metal layers in the interconnect structure and is located at an uppermost extent of the bond pad opening.Type: GrantFiled: December 6, 2019Date of Patent: February 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang, Shih Pei Chou
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Publication number: 20200243580Abstract: A method for manufacturing an image sensing device includes forming an interconnection layer over a front surface of a semiconductor substrate. A trench is formed to extend from a back surface of the semiconductor substrate. An etch stop layer is formed along the trench. A buffer layer is formed over the etch stop layer. An etch process is performed for etching the buffer layer. The buffer layer and the etch stop layer include different materials.Type: ApplicationFiled: April 8, 2020Publication date: July 30, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chuang Wu, Ming-Tsong Wang, Feng-Chi Hung, Ching-Chun Wang, Jen-Cheng Liu, Dun-Nian Yaung
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Publication number: 20200152675Abstract: Some embodiments relate an integrated circuit (IC). The IC includes a first substrate including an array of photodetectors, wherein a bond pad opening extends through the first substrate and is defined by an inner sidewall of the first substrate. An interconnect structure is disposed over the first substrate and includes a plurality of metal layers stacked over one another and disposed within a dielectric structure. The bond pad opening further extends through at least a portion of the interconnect structure and is further defined by an inner sidewall of the interconnect structure. A bond pad structure directly contacts a metal layer of the plurality of metal layers in the interconnect structure and is located at an uppermost extent of the bond pad opening.Type: ApplicationFiled: December 6, 2019Publication date: May 14, 2020Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang, Shih Pei Chou
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Patent number: 10622394Abstract: The image sensing device includes a semiconductor substrate, an interconnection layer, a radiation-sensing region and an isolation structure. The semiconductor substrate has a front surface and a back surface. The interconnection layer is disposed over the front surface of the semiconductor substrate. The radiation-sensing region is disposed in the semiconductor substrate. The isolation structure is disposed on the back surface of the semiconductor substrate. The isolation structure includes a trench and an etch stop layer. The trench extends from the back surface of the semiconductor substrate. The etch stop layer is disposed along the trench. An etch selectivity of a silicon oxide film to the etch stop layer is greater than a predetermined value.Type: GrantFiled: May 10, 2017Date of Patent: April 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chuang Wu, Ming-Tsong Wang, Feng-Chi Hung, Ching-Chun Wang, Jen-Cheng Liu, Dun-Nian Yaung
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Patent number: 10515995Abstract: Some embodiments relate to a method. In the method, a CMOS substrate, which includes a plurality of CMOS devices, is received. An interconnect structure including a plurality of metal layers is formed over the CMOS substrate, wherein a first metal layer of the metal layers is nearest the CMOS substrate and an Nth of the metal layers is furthest from the CMOS substrate. An image sensor substrate is bonded to the interconnect structure. A first mask is formed over the image sensor substrate, and a first etch is performed with the first mask in place to expose an upper surface of the first metal layer. A conductive bond pad material is formed in direct contact with the exposed first metal layer.Type: GrantFiled: July 24, 2018Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang, Shih Pei Chou
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Patent number: 10304889Abstract: The present disclosure provides a method of manufacturing an image sensor device. The method comprises forming a first semiconductor chip including a matrix of image sensing cells and bonding a second semiconductor chip with the first semiconductor chip. A plurality of conductive vias are formed in the second semiconductor chip, where each of the plurality of conductive vias includes a first end substantially coplanar with a first surface of the first semiconductor chip and a second end in contact with a conductive trace in the second semiconductor chip. A first dielectric layer is formed over the plurality of conductive vias and a first conductive material is formed over the first dielectric layer. The first conductive material is etched to form a plurality of conductors coupled to ground and the plurality of conductors are electrically isolated from one another.Type: GrantFiled: June 8, 2017Date of Patent: May 28, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei Chuang Wu, Ming-Tsong Wang, Feng-Chi Hung, Jen-Cheng Liu, Ching-Chun Wang
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Publication number: 20180350857Abstract: Some embodiments relate to a method. In the method, a CMOS substrate, which includes a plurality of CMOS devices, is received. An interconnect structure including a plurality of metal layers is formed over the CMOS substrate, wherein a first metal layer of the metal layers is nearest the CMOS substrate and an Nth of the metal layers is furthest from the CMOS substrate. An image sensor substrate is bonded to the interconnect structure. A first mask is formed over the image sensor substrate, and a first etch is performed with the first mask in place to expose an upper surface of the first metal layer. A conductive bond pad material is formed in direct contact with the exposed first metal layer.Type: ApplicationFiled: July 24, 2018Publication date: December 6, 2018Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang, Shih Pei Chou
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Patent number: 10074680Abstract: A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof.Type: GrantFiled: March 4, 2016Date of Patent: September 11, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsien Tseng, Nai-Wen Cheng, Shou-Gwo Wuu, Ming-Tsong Wang, Tung-Ting Wu
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Publication number: 20180240835Abstract: The present disclosure provides a method of manufacturing an image sensor device. The method comprises forming a first semiconductor chip including a matrix of image sensing cells and bonding a second semiconductor chip with the first semiconductor chip. A plurality of conductive vias are formed in the second semiconductor chip, where each of the plurality of conductive vias includes a first end substantially coplanar with a first surface of the first semiconductor chip and a second end in contact with a conductive trace in the second semiconductor chip. A first dielectric layer is formed over the plurality of conductive vias and a first conductive material is formed over the first dielectric layer. The first conductive material is etched to form a plurality of conductors coupled to ground and the plurality of conductors are electrically isolated from one another.Type: ApplicationFiled: June 8, 2017Publication date: August 23, 2018Inventors: WEI CHUANG WU, MING-TSONG WANG, FENG-CHI HUNG, JEN-CHENG LIU, CHING-CHUN WANG
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Patent number: 10038026Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3DIC includes a first substrate including a photodetector which is configured to receive light in a first direction from a light source. An interconnect structure is disposed over the first substrate, and includes a plurality of metal layers and insulating layers that are over stacked over one another in alternating fashion. One of the plurality of metal layers is closest to the light source and another of the plurality of metal layers is furthest from the light source. A bond pad recess extends into the interconnect structure from an opening in a surface of the 3DIC which is nearest the light source and terminates at a bond pad. The bond pad is spaced apart from the surface of the 3DIC and is in direct contact with the one of the plurality of metal layers that is furthest from the light source.Type: GrantFiled: April 1, 2016Date of Patent: July 31, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang, Shih Pei Chou
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Publication number: 20180158850Abstract: The image sensing device includes a semiconductor substrate, an interconnection layer, a radiation-sensing region and an isolation structure. The semiconductor substrate has a front surface and a back surface. The interconnection layer is disposed over the front surface of the semiconductor substrate. The radiation-sensing region is disposed in the semiconductor substrate. The isolation structure is disposed on the back surface of the semiconductor substrate. The isolation structure includes a trench and an etch stop layer. The trench extends from the back surface of the semiconductor substrate. The etch stop layer is disposed along the trench. An etch selectivity of a silicon oxide film to the etch stop layer is greater than a predetermined value.Type: ApplicationFiled: May 10, 2017Publication date: June 7, 2018Inventors: Wei-Chuang WU, Ming-Tsong WANG, Feng-Chi HUNG, Ching-Chun WANG, Jen-Cheng LIU, Dun-Nian YAUNG
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Patent number: 9536810Abstract: A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided.Type: GrantFiled: June 12, 2015Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Hsiao-Hui Tseng, Ming-Tsong Wang, Shyh-Fann Ting, Wei Chuang Wu
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Publication number: 20160379962Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3DIC includes a first substrate including a photodetector which is configured to receive light in a first direction from a light source. An interconnect structure is disposed over the first substrate, and includes a plurality of metal layers and insulating layers that are over stacked over one another in alternating fashion. One of the plurality of metal layers is closest to the light source and another of the plurality of metal layers is furthest from the light source. A bond pad recess extends into the interconnect structure from an opening in a surface of the 3DIC which is nearest the light source and terminates at a bond pad. The bond pad is spaced apart from the surface of the 3DIC and is in direct contact with the one of the plurality of metal layers that is furthest from the light source.Type: ApplicationFiled: April 1, 2016Publication date: December 29, 2016Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang, Shih Pei Chou
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Publication number: 20160365378Abstract: A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided.Type: ApplicationFiled: June 12, 2015Publication date: December 15, 2016Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Hsiao-Hui Tseng, Ming-Tsong Wang, Shyh-Fann Ting, Wei Chuang Wu
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Publication number: 20160190190Abstract: A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Inventors: Chien-Hsien Tseng, Nai-Wen Cheng, Shou-Gwo Wuu, Ming-Tsong Wang, Tung-Ting Wu
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Patent number: 9299740Abstract: A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof.Type: GrantFiled: October 12, 2012Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsien Tseng, Nai-Wen Cheng, Shou-Gwo Wuu, Ming-Tsong Wang, Tung-Ting Wu