Patents by Inventor Ming-Tsong Wang
Ming-Tsong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9299740Abstract: A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof.Type: GrantFiled: October 12, 2012Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsien Tseng, Nai-Wen Cheng, Shou-Gwo Wuu, Ming-Tsong Wang, Tung-Ting Wu
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Patent number: 8816422Abstract: A semiconductor device includes a semiconductor substrate, a top gate over the semiconductor substrate, and a stacked gate between the top gate and the semiconductor substrate. The stacked gate includes a first tunneling layer, a first storage layer adjoining the first tunneling layer, and an additional layer adjoining the first tunneling layer. The additional layer is selected from the group consisting of a retention layer and an additional composite layer. The additional composite layer comprises a second tunneling layer and a second storage layer adjoining the second tunneling layer. The semiconductor device further includes a blocking layer adjoining the first storage layer.Type: GrantFiled: September 15, 2006Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Tsong Wang, Tong-Chern Ong
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Patent number: 8735963Abstract: A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band.Type: GrantFiled: July 7, 2008Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Tsong Wang, Tong-Chern Ong, Albert Chin, Hsueh-Jen Yang
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Publication number: 20130320469Abstract: A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof.Type: ApplicationFiled: October 12, 2012Publication date: December 5, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsien Tseng, Nai-Wen Cheng, Shou-Gwo Wuu, Ming-Tsong Wang, Tung-Ting Wu
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Patent number: 8294197Abstract: A flash memory cell includes a substrate, a blocking layer over the substrate, a floating gate over the blocking layer, a retention layer over the floating gate, a control gate over the retention layer, a tunneling layer over the control gate, a top gate over the tunneling layer, and a voltage source electrically coupled between the top gate and the control gate. Various charge tunneling mechanisms may be used for charges to tunnel through the retention layer.Type: GrantFiled: September 22, 2006Date of Patent: October 23, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Tsong Wang, Tong-Chern Ong
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Patent number: 8212233Abstract: An integrated circuit structure includes a dielectric layer having an upper portion and a lower portion. The dielectric layer is either an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD). A phase change random access memory (PCRAM) cell includes a phase change strip, wherein the phase change strip is on the lower portion and has a top surface lower than a top surface of the dielectric layer, and a bottom surface higher than a bottom surface of the dielectric layer. A first conductive column is electrically connected to the phase change strip. The first conductive column extends from the top surface of the dielectric layer down into the dielectric layer. A second conductive column is in a peripheral region. The second conductive column extends from the top surface of the dielectric layer down into the dielectric layer. The first conductive column and the second conductive column have different heights.Type: GrantFiled: February 26, 2010Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Tsong Wang, Chien-Chih Chiu, Tsun Kai Tsao, Chi-Hsin Lo
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Patent number: 7968967Abstract: A semiconductor structure includes a semiconductor substrate, a power source, and a stacked structure over the semiconductor substrate and coupled to the power source. The stacked structure includes a bottom electrode, a top electrode, and an insulation layer between the top electrode and the bottom electrode, wherein the insulation layer has a breakdown voltage lower than a pre-determined write voltage provided by the power source and higher than a pre-determined read voltage provided by the power source.Type: GrantFiled: July 17, 2006Date of Patent: June 28, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Tsong Wang, Tong-Chern Ong
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Publication number: 20100301303Abstract: An integrated circuit structure includes a dielectric layer having an upper portion and a lower portion. The dielectric layer is either an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD). A phase change random access memory (PCRAM) cell includes a phase change strip, wherein the phase change strip is on the lower portion and has a top surface lower than a top surface of the dielectric layer, and a bottom surface higher than a bottom surface of the dielectric layer. A first conductive column is electrically connected to the phase change strip. The first conductive column extends from the top surface of the dielectric layer down into the dielectric layer. A second conductive column is in a peripheral region. The second conductive column extends from the top surface of the dielectric layer down into the dielectric layer. The first conductive column and the second conductive column have different heights.Type: ApplicationFiled: February 26, 2010Publication date: December 2, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Tsong Wang, Chien-Chih Chiu, Tsun Kai Tsao, Chi-Hsin Lo
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Publication number: 20100001335Abstract: A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band.Type: ApplicationFiled: July 7, 2008Publication date: January 7, 2010Inventors: Ming-Tsong Wang, Tong-Chern Ong, Albert Chin, Hsueh-Jen Yang
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Patent number: 7579646Abstract: A flash memory cell includes a substrate and a gate structure formed on the substrate. The gate structure includes a tunneling layer over the substrate, a storage layer over the tunneling layer, a blocking layer over the storage layer, and a gate electrode over the dielectric. The storage layer preferably has a conduction band lower than a conduction band of silicon. The blocking layer is preferably formed of a high-k dielectric material.Type: GrantFiled: May 25, 2006Date of Patent: August 25, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Tsong Wang, Tong-Chern Ong, Albert Chin, Chun-Hung Lai
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Publication number: 20080073689Abstract: A flash memory cell includes a substrate, a blocking layer over the substrate, a floating gate over the blocking layer, a retention layer over the floating gate, a control gate over the retention layer, a tunneling layer over the control gate, a top gate over the tunneling layer, and a voltage source electrically coupled between the top gate and the control gate. Various charge tunneling mechanisms may be used for charges to tunnel through the retention layer.Type: ApplicationFiled: September 22, 2006Publication date: March 27, 2008Inventors: Ming-Tsong Wang, Tong-Chern Ong
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Publication number: 20080067577Abstract: A semiconductor device includes a semiconductor substrate, a top gate over the semiconductor substrate, and a stacked gate between the top gate and the semiconductor substrate. The stacked gate includes a first tunneling layer, a first storage layer adjoining the first tunneling layer, and an additional layer adjoining the first tunneling layer. The additional layer is selected from the group consisting of a retention layer and an additional composite layer. The additional composite layer comprises a second tunneling layer and a second storage layer adjoining the second tunneling layer. The semiconductor device further includes a blocking layer adjoining the first storage layer.Type: ApplicationFiled: September 15, 2006Publication date: March 20, 2008Inventors: Ming-Tsong Wang, Tong-Chern Ong
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Publication number: 20080012138Abstract: A semiconductor structure includes a semiconductor substrate, a power source, and a stacked structure over the semiconductor substrate and coupled to the power source. The stacked structure includes a bottom electrode, a top electrode, and an insulation layer between the top electrode and the bottom electrode, wherein the insulation layer has a breakdown voltage lower than a pre-determined write voltage provided by the power source and higher than a pre-determined read voltage provided by the power source.Type: ApplicationFiled: July 17, 2006Publication date: January 17, 2008Inventors: Ming-Tsong Wang, Tong-Chern Ong
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Patent number: 7316240Abstract: An exhaust system and a mini-exhaust static pressure controlling apparatus thereof for controlling a process area. The mini-exhaust static pressure controlling apparatus has an exhaust chamber and an auto release damping device. The exhaust chamber has an air inlet connected to the process area receiving air exhaust from the process area, and an air outlet venting the air exhaust. The auto release damping device has a diaphragm pre-stressed in an arc shape with a coefficient of elasticity and an adjusting device for applying a stress on the diaphragm to maintain the arc shape of the diaphragm, and is disposed on the exhaust chamber to control static pressure of the air exhaust in the exhaust chamber.Type: GrantFiled: April 21, 2005Date of Patent: January 8, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Sung Kuo, Yung-Dar Chen, Dar-Rung Kuo, Ming-Chien Wen, Ming-Tsong Wang
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Publication number: 20070272916Abstract: A flash memory cell includes a substrate and a gate structure formed on the substrate. The gate structure includes a tunneling layer over the substrate, a storage layer over the tunneling layer, a blocking layer over the storage layer, and a gate electrode over the dielectric. The storage layer preferably has a conduction band lower than a conduction band of silicon. The blocking layer is preferably formed of a high-k dielectric material.Type: ApplicationFiled: May 25, 2006Publication date: November 29, 2007Inventors: Ming-Tsong Wang, Tong-Chern Ong, Albert Chin, Chun-Hung Lai
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Publication number: 20060237073Abstract: An exhaust system and a mini-exhaust static pressure controlling apparatus thereof for controlling a process area. The mini-exhaust static pressure controlling apparatus has an exhaust chamber and an auto release damping device. The exhaust chamber has an air inlet connected to the process area receiving air exhaust from the process area, and an air outlet venting the air exhaust. The auto release damping device has a diaphragm pre-stressed in an arc shape with a coefficient of elasticity and an adjusting device for applying a stress on the diaphragm to maintain the arc shape of the diaphragm, and is disposed on the exhaust chamber to control static pressure of the air exhaust in the exhaust chamber.Type: ApplicationFiled: April 21, 2005Publication date: October 26, 2006Inventors: Po-Sung Kuo, Yung-Dar Chen, Dar-Rung Kuo, Ming-Chien Wen, Ming-Tsong Wang
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Publication number: 20050059233Abstract: A process for forming a metal damascene structure. First, a cap layer is formed on a first metal layer, and a dielectric layer is formed on the cap layer. Next, the dielectric layer is etched to form a damascene opening. Next, hydrogen-containing plasma, nitrogen-containing plasma, oxygen-containing plasma, or a mixture thereof is used to perform the plasma treatment. Next, a metal is filled in the damascene opening to form a second metal layer. Peeling of the dielectric layer due to remaining impurities is eliminated by the plasma treatment after etching of the damascene opening.Type: ApplicationFiled: September 12, 2003Publication date: March 17, 2005Inventors: Ming-Tsong Wang, Di-Shi Su, Chia-Ming Yang, Ching-Ming Tsai
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Publication number: 20040098949Abstract: A new and improved method for packaging substrates for shipping or transport. The method of the invention comprises a primary packaging structure in which the substrates are placed in a suitable substrate container; a secondary packaging structure in which the substrate container of the primary packaging structure is vacuum-sealed in an anti-static bag; a tertiary packaging structure in which the secondary packaging structure is fitted with a resilient cushion; and a quaternary or final packaging structure in which the tertiary packaging structure is sealed in a shipping carton.Type: ApplicationFiled: November 21, 2002Publication date: May 27, 2004Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Shen-Yau Huang, Ming-Chen Tai, Ming-Tsong Wang, Tai-Yau Shen
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Patent number: 6660125Abstract: A new method is provided for the removal of metal residue or nodules from surfaces that are target surfaces during the process of metal sputtering. A polishing bit is applied in a rotating manner to a surface on which nodules have been formed, this application removes the nodules from the target surface and prepares the surface for further processing steps.Type: GrantFiled: December 31, 2001Date of Patent: December 9, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ming-Tsong Wang, Chung-En Kao, Kuang-Hsing Liu, Ta-Bin Chen
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Patent number: 6566263Abstract: A method of forming an HDP CVD oxide layer over a metal line structure, comprising the following steps. A semiconductor structure having metal lines formed thereon to form a metal line structure is provided. The metal lines having exposed sidewalls. The metal line structure is treated with N2O to form a layer of Al2O3 on each of the metal line exposed sidewalls to form a N2O treated metal line structure. An HDP CVD oxide layer is formed over the N2O treated metal line structure to form a resulting metal line structure. Whereby the resulting metal line structure is free of metal voids.Type: GrantFiled: August 2, 2000Date of Patent: May 20, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Mong-Chi Hung, Ming-Tsong Wang, Teh-Wei Ger