Abstract: An apparatus is provided that includes a memory die having a first memory cell, and a controller connected to the memory die. The controller is configured to apply a plurality of programming pulses to the first memory cell, apply a plurality of first verify pulses to the first memory cell, determine from the first verify pulses that the first memory cell has been programmed to a first programmed memory state, apply a single second verify pulse to the first memory cell after determining that the first memory cell has been programmed to the first programmed memory state, determine from the single second verify pulse that the first memory cell is no longer programmed to the first programmed memory state, and apply an additional programming pulse to the first memory cell.

Abstract: A method for performing channel usage management with aid of multi-link operation architecture and associated apparatus are provided. The method applicable to a wireless transceiver device within a wireless communications system may include: utilizing the wireless transceiver device to communicate with another device within the wireless communications system through at least one portion of multiple links respectively corresponding to multiple predetermined radio frequency bands; and at first time point when radar is detected in a first channel used by a first link among the multiple links, starting performing a first procedure to make channel management information be received by the other device via one or more other links among the multiple links at any time point when the other device is ready to receive the channel management information, wherein the other device is not ready to receive the channel management information at the first time point.

Abstract: The present invention provides a heating device and a control method thereof. The heating device includes an electromagnetic wave generating module and a matching module. The control method includes: controlling an electromagnetic wave generating module to generate an electromagnetic wave signal of a preset heating power; and determining a load matching degree of the electromagnetic wave generating module, and adjusting impedance of the matching module based on the load matching degree. When the load matching degrees determined within a preset adjustment time are all less than or equal to a first matching threshold, the electromagnetic wave generating module is controlled to stop working, such that the object to be processed that contains more components having a poor electromagnetic wave absorption capacity is prevented from being continuously heated after its moisture has been converted from ice to liquid.

Abstract: Provided are a display unit and a display apparatus, the display unit includes a back plate and a print circuit board disposed on the back plate, wherein the print circuit board is connected to the back plate through a screw, and is provided with a first electrostatic discharge region and a first electrostatic discharge unit; the first electrostatic discharge region is connected to the back plate through the screw to form a first electrostatic discharge channel, and the first electrostatic discharge unit is connected to the back plate to form a second electrostatic discharge channel.

Abstract: A preparation method of a positive electrode material of a lithium battery is provided, including mixing a compound containing at least one ethylenically-unsaturated group and one carbonyl group or a derivative thereof and a Ni-rich oxide of lithium and transition metal to react. The compound containing at least one ethylenically-unsaturated group and one carbonyl group is selected from a group consisting of a maleimide-based compound, an acrylate-based compound, a methacrylate-based compound, an acrylamide-based compound, a vinylamide-based compound, and a combination thereof, and the Ni-rich oxide of lithium and transition metal is represented by formula I, LiNixMyO2 ??Formula I wherein x+y=1, 1>x?0.5, and M is at least one transition metal element except Ni.

Abstract: Technology is disclosed herein for open block boundary group programming of non-volatile memory such as NAND. The open block boundary group could potentially be read in response to a request from a host for the data stored in the group. In an aspect, the memory system will determine whether programming a group of memory cells in a selected block will result in an open block. If it will not result in an open block, then the memory system uses a first set of programming parameters to program the group. However, if it will result in an open block then the memory system uses a second set of programming parameters to program the boundary group. The programming parameters may include verify levels and/or a program voltage step size. The second set of programming parameters can tighten Vt distributions, which mitigates mis-reads if the boundary group is read.

Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, thermal silicon substrates and an encapsulation is provided. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The thermal silicon substrates are disposed on the first semiconductor die, wherein the thermal silicon substrates are spaced apart from the second semiconductor die. The encapsulation is disposed on the first semiconductor die. The encapsulation encapsulates the second semiconductor die and the thermal silicon substrates. The encapsulation includes a filling material layer and an insulator, wherein the filling material layer is disposed on the first semiconductor die and located between the second semiconductor die and thermal silicon substrates, and the filling material layer is spaced apart from the second semiconductor die and the thermal silicon substrates by the insulator.

Abstract: The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in strings and are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages associated with the data states targeted for each of the memory cells being programmed during verify loops of a program-verify operation. The control means slows the memory cells targeted for a selected one of the data states identified as being faster to program than other ones of the memory cells during one of verify loops associated with an earlier one of data states.

Abstract: The present disclosure provides a light guide plate, including a light-entering surface, a light-exiting surface adjacent to the light-entering surface, and a bottom surface arranged opposite to the light-exiting surface. The light guide plate includes a central region corresponding to an active display region of a display panel and a peripheral region corresponding a non-display region of the display panel in a first direction, the peripheral region includes a first peripheral region at a side adjacent to the light-entering surface, at least the first peripheral region of the peripheral region has a thickness smaller than the central region in a second direction, the first direction is a direction in which light is propagated inside the light guide plate, and the second direction is a direction in which the light exits the light guide plate. The present disclosure further provides a backlight module and a display device.

Abstract: The present invention relates to an antibody binding to lymphocyte activation gene-3 (LAG-3) and use thereof.

Abstract: Disclosed are a self-positioning assembly system for rapid assembly of an aircraft and a method thereof. The self-positioning assembly system includes a mounting platform, a framework assembly, a hole positioner assembly, a strut positioner assembly and a pallet assembly. The framework assembly is mounted on the mounting platform and includes a hole positioner column and a pallet column, the hole positioner assembly is arranged on the hole positioner column, the pallet assembly is arranged on the pallet column, a plurality of the hole positioner columns are respectively arranged on both sides of the mounting platform, and a plurality of the pallet columns are arranged in a middle of the mounting platform.

Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.

Abstract: A fluid collecting apparatus includes a housing, a gripping member, an inlet, and an outlet. The housing includes a chamber. The gripping member is movable within the chamber, extendable toward or retractable away from a tank, and is configured to hold a computing device. The inlet is communicable with the chamber and configured to deliver a gas into the chamber. The outlet is communicable with the chamber and configured to discharge the gas out of the chamber. A method of operating a cooling system includes receiving the tank, a coolant held by the tank, and a computing device immersed in the coolant, disposing the fluid collecting apparatus over the tank, moving the computing device into the chamber by the gripping member; supplying a gas from the inlet to be blown against the computing device; and discharging the gas and a vaporized coolant out of the chamber through the outlet.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor die, a semiconductor frame structure, a semiconductor cover structure and conductive balls. The substrate has a ground plate embedded therein. The semiconductor die is disposed on the substrate and electrically connected with the substrate. The semiconductor frame structure is disposed on the substrate and surrounds the semiconductor die. The semiconductor frame structure includes conductive through semiconductor vias (TSVs) penetrating through the semiconductor frame structure, and at least one conductive TSV is electrically connected with the ground plate. The semiconductor cover structure is disposed on the semiconductor frame structure and on the semiconductor die. The semiconductor cover structure includes a conductive grid pattern and the conductive grid pattern contacts the conductive TSVs.

Abstract: A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an optical device within or on a semiconductor substrate. A light guide structure overlies the optical device. A first etch stop layer extends along first sidewalls and a lower surface of the light guide structure. A second etch stop layer overlies the first etch stop layer and extends along second sidewalls of the light guide structure.

Abstract: A fluid collecting apparatus includes a housing, a gripping member, an inlet, and an outlet. The housing includes a chamber. The gripping member is movable within the chamber, extendable toward or retractable away from a tank, and is configured to hold a computing device. The inlet is communicable with the chamber and configured to deliver a gas into the chamber. The outlet is communicable with the chamber and configured to discharge the gas out of the chamber. A method of operating a cooling system includes receiving the tank, a coolant held by the tank, and a computing device immersed in the coolant, disposing the fluid collecting apparatus over the tank, moving the computing device into the chamber by the gripping member; supplying a gas from the inlet to be blown against the computing device; and discharging the gas and a vaporized coolant out of the chamber through the outlet.

Abstract: Methods of fabricating solar cells having a plurality of sub-cells coupled by cell level interconnection, and the resulting solar cells, are described herein. In an example, a solar cell includes a plurality of sub-cells. Each of the plurality of sub-cells includes a singulated and physically separated semiconductor substrate portion. Each of the plurality of sub-cells includes an on-sub-cell metallization structure interconnecting emitter regions of the sub-cell. An inter-sub-cell metallization structure couples adjacent ones of the plurality of sub-cells. The inter-sub-cell metallization structure is different in composition from the on-sub-cell metallization structure.

Abstract: In a method for manufacturing a memory device, a plurality of first insulating layers and a bottom select gate (BSG) layer are formed over a substrate, where the first insulating layers are disposed between the substrate and the BSG layer. One or more first dielectric trenches are formed to pass through the BSG layer and the first insulating layers, and extend in a length direction of the substrate. A plurality of word line layers and a plurality of second insulating layers are formed over the BSG layer, where the second insulating layers are disposed between the BSG layer and the word line layers. One or more common source regions are formed over the substrate to extend in the length direction of the substrate, and further extend through the BSG layer, the first insulating layers, the word line layers, and the second insulating layers.