Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: An ambulance-type mobile catheter room for cardiovascular interventional surgery enables interventional diagnosis and treatment devices for acute and severe cardiovascular diseases to be deployed quickly, is flexible and high in adaptability, and provides hardware devices for cardiovascular diagnosis and treatment interventional surgeons to timely diagnose and treat patients. The ambulance-type mobile catheter room for cardiovascular interventional surgery includes an ambulance. The ambulance is internally provided with an antibacterial internal environment, a robotic angiography machine system, a wireless medical Internet of Things system, a self-generating system and an auxiliary system.

Abstract: A method for inspecting authenticity of a hologram is provided. A computer device that stores a color image of the hologram transforms the color image into a hyperspectral image, converts the hyperspectral image into a grayscale image, and determines authenticity of the hologram based on multiple grayscale values in a region of interest in the grayscale image and multiple grayscale thresholds that respectively correspond to different wavelengths.

Abstract: A memory device includes at least one bit line, at least one word line, at least one memory cell, at least one source line, and a controller electrically coupled to the at least one memory cell via the at least one word line, the at least one bit line, and the at least one source line. The memory cell includes a first transistor, data storage elements, and second transistors corresponding to the data storage elements. The first transistor includes a gate electrically coupled to the word line, and first and second source/drains. Each data storage element and the corresponding second transistor are electrically coupled in series with the first source/drain of the first transistor and the bit line. The controller controllably applies a voltage other than a ground voltage to the at least one source line in an operation of a selected data storage element among the data storage elements.

Abstract: An electronic device such as a voice-controlled speaker may have an array of strain gauges and light-emitting diodes. The light-emitting diodes may be configured to display dynamically adjustable button icons overlapping the strain gauges. Force measurements from the strain gauges may be used to adjust speaker output and other device operations.

Abstract: A drill bit for cutting formation comprises a bit body, a plurality of cutters, and a plurality of blades with pockets to accommodate the cutters, respectively. Each of the plurality of cutters has a substrate, an ultra-hard layer, an inclined surface on the top of the ultra-hard layer, wherein the inclined surface slants downward from a cutting edge to a trailing edge. The cutter can improve cutting efficiency and service life.

Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: Systems and methods for electronic displays to use reference voltages to control driving current of illuminators are provided. The reference voltages are used to reduce or eliminate cross talk in driving voltages among different illuminators and driving voltage variations from frame to frame. The transient performance of the driving current of the illuminator (e.g., the current rise/decline time, current overshoot issue, current settling time) may be improved by implementing the reference voltages.

Abstract: A light emitting substrate is provided. The light emitting substrate includes a plurality of light emitting controlling units arranged in M rows and N columns, M is an integer equal to or greater than one, N is an integer equal to or greater than one, wherein a respective one of the plurality of light emitting controlling units includes a plurality of light emitting elements arranged in J rows and I columns, J being an integer equal to or greater than one, I being an integer equal to or greater than one, a i-th column of the I columns of light emitting elements includes J rows of light emitting elements, 1?i?I; (M×J) number of first voltage signal lines; and (M×J) number of groups of second voltage signal lines.

Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

Abstract: Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: A device for detecting a slot wedge, an air gap and a broken rotor bar is provided, where a sequential circuit generates double concurrent pulses; the sequential circuit is connected to driving power modules; the driving power modules are connected to front-end interface circuits; the front-end interface circuits convert the double concurrent pulses into corresponding magnetic-field pulses; the magnetic-field pulses are transmitted to power supply terminals on adjacent phases of stator windings through impedance matching pins and coupled at a corresponding coil, air gap and squirrel cage rotor to generate single groups of cyclic rotating magnetic potentials; single rotating magnetic potentials are sequentially generated in adjacent slots on each of the phases of the stator windings; rotating electric potentials in magnetic circuits with two symmetrical phases are magnetically coupled to form distributed coupling magnetic field reflected full-cycle waves for reflecting a difference of a corresponding slot wedg

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: A lamp including electrical leads extending into a supporting stem that are in communication with a base electrode for engagement to a light fixture; and a light engine comprising light emitting diode filaments that are in electrical communication with the electrical leads. The light emitting diode filaments including a circuit having a plurality of contact pads arranged along a length of a substrate. The light emitting diode filaments further include light emitting diode (LED) chips engaged to the contact pads along the length of the substrate to provide that the light emitting diode (LED) chips are electrically connected in series. In some embodiments, each light emitting diode (LED) chip includes at least a light transmission surface that is in contact with an individual portion of phosphor for the LED chip. In other embodiments, a phosphor layer extends over an island of LED chips.