Patents by Inventor Ming Wu

Ming Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210134955
    Abstract: A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Jia-Heng Wang, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20210134663
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Application
    Filed: September 30, 2020
    Publication date: May 6, 2021
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Publication number: 20210135102
    Abstract: A semiconductor memory structure includes a memory cell, an encapsulation layer over a sidewall of the memory cell, and a nucleation layer between the sidewall of the memory cell and the encapsulation layer. The memory cell includes a top electrode, a bottom electrode and a data-storage element sandwiched between the bottom electrode and the top electrode. The nucleation layer includes metal oxide.
    Type: Application
    Filed: April 9, 2020
    Publication date: May 6, 2021
    Inventors: HSING-LIEN LIN, FU-TING SUNG, CHING JU YANG, CHII-MING WU
  • Publication number: 20210128559
    Abstract: The invention relates to quinazoline compounds, the preparation method, use, and the pharmaceutical composition thereof. The said quinazoline compounds, which are represented by Formula (I), are phosphatidylinositol 3-kinase (PI3K) inhibitors, and can be applied to prevent and/or treat PI3K activity-related diseases, such as cancer, immune diseases, cardiovascular diseases, viral infections, inflammation, metabolism/endocrine function disorders or neurological diseases.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 6, 2021
    Inventors: Heng XU, Xiaoguang CHEN, Songwen LIN, Ming JI, Jing JIN, Deyu WU, Chunyang WANG, Yuanhao LV
  • Publication number: 20210134694
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Application
    Filed: February 10, 2020
    Publication date: May 6, 2021
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Publication number: 20210124894
    Abstract: An optical image recognition device and a method for fabricating the same are disclosed. The device includes a flexible printed circuit board, an image sensor, a glue, an optical collimator, a supporting ring, a sealant, and an optical filter. The top of the flexible printed circuit board is provided with a recess, the image sensor is located in the recess, the sidewalls of the image sensor and the recess are separated from each other, and the image sensor is coupled to the flexible printed circuit board through conductive wires. The glue adheres to the flexible printed circuit board and the image sensor and covers the conductive wires. The optical collimator is disposed on the image sensor. The supporting ring, disposed on the flexible printed circuit board, surrounds the glue and the optical collimator. The optical filter, disposed on the sealant, shields the optical collimator and the image sensor.
    Type: Application
    Filed: February 14, 2020
    Publication date: April 29, 2021
    Inventors: CHUN-TE CHANG, CHUNG-WU LIU, MING CHANG YU, CHIA YUAN WU
  • Patent number: 10989968
    Abstract: An optical element configured to allow an image beam passing through is provided. The optical element includes a first and a second birefringent layer and a gas layer between the first and the second birefringent layer. An extension direction of the gas layer is inclined with respect to an extension direction of the optical element, wherein the image beam passes through the first birefringent layer, the gas layer and the second birefringent layer in sequence. A first and a second sub image beam having different deflection angles are generated from the image beam when the image beam enters the gas layer. After the first and the second sub image beam are emitted from the second birefringent layer, a transmission path of the first and the second sub image beam are offset from each other by an offset distance, thereby improving resolution of an image to be viewed.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 27, 2021
    Assignee: Coretronic Corporation
    Inventors: Yi-Pai Huang, Tai-Hsiang Jen, Po-Yuan Hsieh, Jui-Yi Wu, Fu-Ming Chuang
  • Patent number: 10988574
    Abstract: A method of producing an oligomer or polymer with carbonate segment chemical structure, the method including the steps of (1) introducing into a reactor high-molecular-weight polyester and reactive oligomer; (2) introducing into the reactor a carbonate compound and a catalyst such that the poly(polyol) reacts with the carbonate monomers by one-pot in situ to produce a crude product; and (3) introducing the crude product into water to obtain an oligomer or polymer with carbonate segment chemical structure. The oligomer or polymer with carbonate segment chemical structure is applicable to automobile manufacturing, wires & cables, and medical equipment.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: April 27, 2021
    Assignee: J & A TECHNOLOGY CORPORATION
    Inventors: Jiang-Jen Lin, Tzong-Ming Lee, Chyi-Ming Leu, Sheng-Yen Shen, Hsin-Chung Wu, Hsuan-Hao Tien
  • Patent number: 10990623
    Abstract: An information retrieval method, an electronic device and a storage medium are provided. The method comprises: sending at least one keyword in chatting contents in an input box of an instant messenger to a server, when it is detected that the chatting contents need to be sent to a communication counterpart; receiving, from the server based on the at least one keyword, retrieved contents and at least one category in which the retrieved contents are categorically stored in the server; and categorically displaying the retrieved contents in a current interface, in accordance with the at least one category.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: April 27, 2021
    Assignee: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
    Inventors: Ming Liu, Liangxiong Wu, Baolin Wang
  • Patent number: 10991824
    Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: April 27, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
  • Patent number: 10990203
    Abstract: In one example, touchpad assembly is disclosed, which may include a bottom cover, a horizontal elastic member flexibly positioned on the bottom cover, a balancing bar disposed on the bottom cover and substantially parallel to the horizontal elastic member, and a metal dome. The metal dome may include a first end fixedly connected to the bottom cover via a first fixture, and a second end to hold the horizontal elastic member and the balancing bar such that the balancing bar is flexibly engaged with the bottom cover. The balancing bar, the metal dome, and the horizontal elastic member may control a flexure of a touchpad when the touchpad is pressed.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 27, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hung-Ming Chen, Chao-Wen Cheng, Kuan-Ting Wu
  • Publication number: 20210120695
    Abstract: An adaptor assembly for an OCP 2.0 form factor card for installation in a server having a side slot to accommodate OCP 3.0 form factor cards is disclosed. The adaptor assembly has an adaptor board allowing the attachment of the OCP 2.0 form factor. The adaptor board includes a socket mateable with a connector on the OCP 2.0 form factor and an edge connector mateable with a socket on the server. The assembly includes an adaptor bracket attachable to the adaptor board. The adaptor bracket has a wall that covers the side slot of the server when the adaptor assembly is inserted through the side slot.
    Type: Application
    Filed: March 17, 2020
    Publication date: April 22, 2021
    Inventors: Yaw-Tzorng TSORNG, Shin-Ming SU, Tung-Hsien WU, Wen-Jui YU
  • Publication number: 20210118125
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 10978771
    Abstract: The present invention discloses a lumped circuit balance converter applied to double-sided parallel lines, comprising a radio frequency transceiver, a balance converter, a filter and a matching network. The filter is connected with the matching network through the balance transmission line. The balance converter comprises a second circuit block, a first circuit block, a third circuit block, a first port, a second port and a third port. A positive polarity of a signal is positioned at the top of the second port and the bottom of the third port. Balance signals are respectively fed to the converter at the top of the second port and the bottom of the third port, and the signals are combined in the first port. The present invention has simple structure and better effect when used, can be easily changed to different required performance, and has good applicability and strong practicability.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 13, 2021
    Assignee: Innovation Sound Technology Co., Ltd.
    Inventors: Shun Ming Yuen, Wai Yin Mung, Ka Ming Wu
  • Patent number: 10978462
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The method includes forming a negative photoresist layer to cover the gate stack and a first portion of the conductive layer over the isolation structure and expose a second portion of the conductive layer. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over the second portion of the conductive layer and an edge portion of the negative photoresist layer, and a thickness of the edge portion decreases in a direction away from the gate stack.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Yen Hsaio, Cheng-Ming Wu, Shih-Lu Hsu, Chien-Hsian Wang
  • Patent number: 10973670
    Abstract: The disclosed embodiments provide an adjustable brace including a first wearable part, a second wearable part, an angle adjustment mechanism and a resistance mechanism. The first wearable part and the second wearable part are pivotably connected to each other via the angle adjustment mechanism and the resistance mechanism.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 13, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tzong-Ming Wu, Ji-Bin Horng, Sung-Ho Liu
  • Publication number: 20210103995
    Abstract: Systems and techniques are described that enable users to interact and share content through a social network application and/or service with other users. In some examples, a social networking system determines that at least two applications are installed on a device and are both useable to share content between a first account and one or more contact accounts. The social networking system may detect an event that causes a change in a badge count, may determine which of the applications to use to display the change, and may output the badge count change to the determined application(s).
    Type: Application
    Filed: January 2, 2020
    Publication date: April 8, 2021
    Inventors: Ryan Michael O'Rourke, Henry Ming Wu, Michael Ross Lewis, Kuan-Yu Tseng, Tae Dong Kim, Zhisheng Huang
  • Publication number: 20210105244
    Abstract: Systems and techniques are described that enable users to interact and share content through a social network application and/or service with other users. A social networking system may determine that a first application and a second application are installed on a device and are both useable to share content between a first account and one or more contact accounts. The social networking system may receive content associated with the first application and the second application and may generate a notification associated with the content. The social networking system may determine which of the first application or the second application to use to present the notification, and may output the notification to the determined first application and/or the second application.
    Type: Application
    Filed: January 2, 2020
    Publication date: April 8, 2021
    Inventors: Ryan Michael O'Rourke, Henry Ming Wu, Michael Ross Lewis, Kuan-Yu Tseng, Tae Dong Kim, Zhisheng Huang
  • Publication number: 20210098859
    Abstract: The present invention belongs to the field of communication technology and discloses a highly elastic antenna made of bonding wires, which comprises a base plate, a line matched transformer, bonding wires, a primary PCB, a secondary PCB and a line inlet. The upper part of the said base plate is provided with a line matched transformer, a bonding wire, a primary PCB and a secondary PCB, one end of the said primary PCB is connected to the line inlet, a line matched transformer is fixed on the upper part of the primary PCB, and the primary PCB is connected to the secondary PCB via bonding wires. In the present invention, bonding wires are employed as a component of antenna radiant elements. As a radiating antenna, the bonding wire may extend into the third dimensional space via its height, thus reducing the space occupied by the antenna on the PCB. One or more bonding wires may be used for different PCB antennas and the resonant frequency may be adjusted by the length or height of the bonding wire.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Chee Kit YUEN, Wai Yin MUNG, Ka Ming WU
  • Publication number: 20210098398
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Julie Yang, Chii-Ming Wu, Tzu-Chung Tsai, Yao-Wen Chang