Abstract: The present invention provides an electroencephalogram measurement structure formed by an ear-hanging structure and a second circuit board. The ear-hanging structure includes a body. An ear-hanging member is disposed at the extension of the body. The body can be worn on the ear via the ear-hanging member. In addition, a first reference electrode and a second reference electrode are disposed on the body and coupled to a first circuit board. The first circuit board is coupled to an electrical jack; the second circuit board is coupled to the electrical jack via an electrical plug. Thereby, the electroencephalogram measurement can be performed simply by wearing the ear-hanging member on the ear of the person under test. Hence, the problems of complicated wiring and inconvenience in wearing can be solved concurrently.

Abstract: A pixel array may include a group of time-of-flight (ToF) sensors. The pixel array may include an image sensor comprising a group of pixel sensors. The image sensor may be arranged among the group of ToF sensors such that the image sensor is adjacent to each ToF sensor in the group of ToF sensors.

Abstract: A memory array includes at least one strap region, at least two sub-arrays, a plurality of staggered, dummy magnetic storage elements, and a plurality of bit line structures. The strap region includes a plurality of source line straps and a plurality of word line straps. The two sub-arrays include a plurality of staggered, active magnetic storage elements. The two sub-arrays are separated by the strap region. The staggered, dummy magnetic storage elements are disposed within the strap region. The bit line structures are disposed in the two sub-arrays, and each of the bit line structures is disposed above and directly connected with at least one of the staggered, active magnetic storage elements.

Abstract: A Schottky diode includes an n-type region, an anode disposed on the n-type region, a buried p-type region, and a shallow p-type region. An interface between the anode and the n-type region forms a Schottky barrier. An n-type channel portion of the n-type region is disposed between the buried p-type region and the shallow p-type region. The anode may also contact the annular shallow p-type region. In an annular configuration, the buried p-type region and the shallow p-type region are annular regions, and the n-type region includes a central portion encircled by the annular shallow p-type region and an annular peripheral portion of the n-type region which encircles the annular shallow p-type region. In one application, a buck converter includes the Schottky diode.

Abstract: A control system may include a direct-current (DC) power bus for charging internal energy storage elements in control devices of the control system. For example, the control devices may be motorized window treatments configured to adjust a position of a covering material to control the amount of daylight entering a space. The system may include a bus power supply that may generate a DC voltage on the DC power bus. For example, the DC power bus may extend from the bus power supply around the perimeter of a floor of the building and may be connected to all of the motorized window treatments on the floor (e.g., in a daisy-chain configuration). An over-power protection circuit may be configured to disconnect the bus power supply if a bus current exceeds a threshold for a period of time.

Abstract: A fabrication method includes: providing a substrate having a front side surface, a back side surface, and a contact pad region; providing an interconnect structure embedded in an interlayer dielectric (ILD) layer below the front side surface of the substrate; forming a first contact pad opening in the contact pad region that extends from above the back side surface through the substrate to an interior area of the ILD layer below the front side surface; forming a contact pad that extends from the first contact pad opening to the interconnect structure; forming an oxide layer over the contact pad; and forming a scribe line pad opening through the oxide layer to the contact pad.

Abstract: The present disclosure, in some embodiments, relates to method. The method includes bonding a second wafer to a first wafer to form a multi-dimensional integrated chip structure. A first edge trimming cut is performed at a first lateral distance from a central region of the multi-dimensional integrated chip structure. A second edge trimming cut is performed at a second lateral distance from the central region of the multi-dimensional integrated chip structure. The second lateral distance is larger than the first lateral distance.

Abstract: A system for rapid bionic entity fitting sampling includes: a processing system; a fitting robot, a shooting component, and a server, all communicatively connected to the processing system; the processing system is configured to obtain a reservation order issued by a user, adjust a body shape of the fitting robot wearing a target garment according to the reservation order, so that the fitting robot wearing the target garment is in a target body shape, and control the shooting component to operate under the target body shape; the shooting component is configured to perform a 360-degree imaging of the fitting robot wearing the target garment to generate an image set corresponding to the target body shape; the processing system is further configured to upload all image sets corresponding to each target garment across all the target body shapes to the server for user access.

Abstract: A method for controlling noise for a human subject comprise receiving an acoustic signal by the human subject through a headphone, the acoustic signal comprising a noise signal, generating a cancellation signal based on a hearing target curve that is related to acoustic magnitude and frequency, and applying the cancellation signal to the acoustic signal such that the noise signal is attenuated.

Abstract: A composite structure includes: a substrate, and a printable layer, provide on at least a part of a surface of the substrate and having accommodated therein a colorful material.

Abstract: A gate-all-around (GAA) high voltage transistor of the laterally double-diffused metal-oxide semiconductor (LDMOS) type has a loop-shaped gate electrode disposed below a surface of a semiconductor substrate. The loop-shaped gate electrode surrounds a vertical channel formed by a first source/drain region, a body region, and a diffusion region. The first source/drain region is on top, the body region is in the middle, and the diffusion region is underneath. A loop-shaped shallow trench isolation (STI) region surrounds the loop-shaped gate electrode. The diffusion region begins inside the loop-shaped gate electrode, extends under the loop-shaped gate electrode and the loop-shaped STI region, and rises outside the loop-shaped STI region to join with a second source/drain region. This structure allows pitch to be reduced by 40% or linear drive current to be doubled in comparison to an asymmetric NMOS transistor providing otherwise equivalent functionality.

Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

Abstract: A functional filament is provided. The functional filament comprises a polymer matrix and functional nanoparticles dispersed within the polymer matrix. The functional filament has a cross-sectional diameter ranging from 1 ?m to 30 ?m, and the functional nanoparticles include element(s) selected from the group consisting of Au, Ag, Ti, Ge, Zn, Al, Mg, Si, Cu, Ca, Fe, Ba, K, Na, Mn, Ni, Ga, Pt, and combinations thereof.

Abstract: A memory structure includes a substrate, a barrier layer, an etch stop layer, a bottom electrode, a data storage feature and a top electrode. The substrate has a metal trench. The barrier layer is disposed over the metal trench. The etch stop layer surrounds the barrier layer, and, together with the barrier layer, completely covers the metal trench. The bottom electrode is disposed over the barrier layer. The data storage feature is disposed over the bottom electrode. The top electrode is disposed over the data storage feature.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region and a gate structure extending into the substrate, wherein a portion of the gate structure below a top surface of the substrate abuts the isolation region. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: Systems and methods are provided for automatically determining an intent of a user based on an intent model to attach a file to a document, prompting the user to confirm the intent using a predetermined character in an inline nudge, generating and displaying an inline menu with an interactive list of ranked files as a suggestion for attachment. The disclosed technology uses the intent for specifying a scope of the inline search. The intent model for attaching content maintained by third-party applications uses a combination of an embeddings model and an N-gram model with limited seed queries and determines the intent based on intent scores associated with respective third-party applications. The present disclosure ranks respective candidate content based on a degree of relevance to the intent. The user selects one or more content from the list for attaching to the document.

Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source/drain region arranged within a substrate. A select gate and a memory gate are arranged over the substrate. An inter-gate dielectric structure is arranged between the memory gate and the select gate. A conductive contact is disposed on the source/drain region and vertically extends from a bottom of the select gate to a top of the select gate. The select gate is closer to the conductive contact than the memory gate. The select gate has a first outermost sidewall that faces away from the memory gate and a second outermost sidewall that faces the memory gate. The first outermost sidewall is taller than the second outermost sidewall.

Abstract: A fabric aluminum composite film structure sequentially includes: a flame-retardant fabric layer, which includes a polyester fabric or a polyamide fabric; a flame-retardant coating layer, which includes polyurethane resin and flame retardants; an adhesive layer, which includes a solvent-free adhesive; an aluminum layer; and a transparent polyester layer. In addition, the fabric aluminum composite film structure has sufficient flammability, which is a flame-retardant fabric with weight reduction and good adhesion suitable for reflecting radar waves from a life raft.

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.