Abstract: An immersion-type heat dissipation structure having high density heat dissipation fins is provided, which includes a heat dissipation substrate and the plurality of sheet-like heat dissipation fins. A thickness of the heat dissipation substrate is from 2 mm to 6 mm, and a bottom surface of the heat dissipation substrate contacts a heating element immersed in a two-phase coolant. The sheet-like heat dissipation fins are integrally formed on an upper surface of the heat dissipation substrate and arranged in high density. A length, a width, and a height of at least one of the sheet-like heat dissipation fins are from 60 mm to 120 mm, from 0.1 mm to 0.5 mm, and from 3 mm to 10 mm, respectively. Further, a distance between at least two of the sheet-like heat dissipation fins that are arranged in parallel to each other is from 0.1 mm to 0.5 mm.

Abstract: A gene sequencing reaction device, a gene sequencing system and a gene sequencing reaction method. The gene sequencing reaction device includes: a supporting platform; a dipping container disposed on the supporting platform, wherein the dipping container has a dipping reaction area, and the dipping reaction area is configured to hold a chemical reagent for gene sequencing reaction, so as to dip a sequencing chip having a DNA sample loading structure on the surface and having a DNA sample loaded thereon in the chemical reagent to perform a gene sequencing reaction; a temperature control apparatus, configured to control the temperature of the chemical reagent in the dipping reaction area; and a transfer apparatus, configured to insert the sequencing chip into the dipping reaction area or pull out the sequencing chip from the dipping reaction area.

Abstract: A radio physical layer protocol data unit (PPDU) sending method includes: obtaining, a radio physical layer protocol data unit (PPDU), wherein the PPDU includes a high efficiency-signal field A (HE-SIG-A) and a high efficiency-signal field B (HE-SIG-B), the HE-SIG-A includes a field indicating a quantity of orthogonal frequency division multiplexing (OFDM) symbols in the HE-SIG-B, and wherein a value of the field indicates one of the following: that the quantity of OFDM symbols included in the HE-SIG-B is greater than or equal to 16, or the quantity of OFDM symbols included in the HE-SIG-B; and sending the PPDU.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: The present application discloses a communication method, a terminal, a server, a communication system, a computer device and a medium. The communication method includes that a server establishes a connection and feeds back a display control in response to requests of a first terminal and a second terminal; then, the server feeds back function feedback information in response to a function request of the first terminal, and feeds back function feedback information in response to a menu request of the second terminal; and the servers presents multiple interface components and maintains and updates each interface component in response to management operation of a third user.

Abstract: An encryption and signature device for AI model protection is provided. The encryption and signature device for AI model protection includes a key derivation unit, a model encryption unit, a model password encryption unit, an image generation unit and a signature unit. The key derivation unit is configured to derive a model key according to a model password and a derivation function. The model encryption unit is configured to encrypt an AI model according to the model key to generate an encrypted AI model. The model password encryption unit is configured to encrypt the model password to generate an encrypted model password. The image generation unit is configured to generate an image file according to the encrypted model password and the encrypted AI model. The signature unit is configured to sign the image file according to a private key to obtain a signed image file.

Abstract: An antenna module includes a first antenna radiator including a feeding terminal, a second antenna radiator, a first ground radiator, a second ground radiator and a capacitive element. The second antenna radiator is disposed on one side of the first antenna radiator, and a first gap is formed between a main portion of the second antenna radiator and the first antenna radiator. The first ground radiator is disposed on another side of the first antenna radiator, and a second gap is formed between the first antenna radiator and the first antenna radiator. The second ground radiator is disposed between the second antenna radiator and the first ground radiator, and a third gap is formed between the second ground radiator and a first branch of the second antenna radiator. The capacitive element is disposed on the third gap and connects the second antenna radiator and the second ground radiator.

Abstract: A pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (NIR) pixel sensors. The color information obtained by the visible light pixel sensors and the luminance obtained by the NIR pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. The capability to accommodate different sizes of visible light pixel sensors and NIR pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.

Abstract: Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: A memory device is provided, including an array of bit cells and a set of tracking cells. The set of tracking cells is arranged adjacent to the array of bit cells along a first direction. The set of tracking cells includes a set of first tracking cells configured to perform a read tracking operation and a set of second tracking cells configured to perform a write tracking operation and arranged adjacent to the set of first tracking cells along a second direction. First tracking cells in the set of first tracking cells are coupled in series with each other and arranged along the second direction, and second tracking cells in the set of second tracking cells are coupled in series with each other and arranged along the second direction.

Abstract: A signal processing system and method for a radiation detector based on a metal oxide semiconductor (MOS) transistor are disclosed. The signal processing system includes a power supply generation module, an analog signal processing module, and a digital signal acquiring-processing module. The power supply generation module provides a novel power supply method, and converts a positive high voltage power supply into a negative high voltage power supply to supply power to a last dynode of a photomultiplier tube (PMT). The analog signal processing module converts a negative current pulse signal into a voltage difference signal. The digital signal acquiring-processing module acquires a signal of the analog signal processing module, and converts the signal into a digital signal for identification.

Abstract: A method includes forming a first trench and a second trench in a semiconductor substrate; forming a first mask over the semiconductor substrate, wherein the first mask is disposed in a first portion of the first trench and exposes the second trench and a second portion of the first trench; after forming the first mask, deepening the second trench and the second portion of the first trench; after deepening the second trench and the second portion of the first trench, removing the first mask; and after removing the first mask, filling a dielectric material in both the first and second trenches.

Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network and multiple host computers executing multiple machines. At a first host computer, the method identifies and stores (i) multiple time values associated with several packet processing operations performed on a particular packet sent by a first machine executing on the first host computer, and (ii) a time value associated with packet transmission through the SDDC network from the first host computer to a second host computer that is a destination of the particular packet. The method provides the stored time values to a set of one or more controllers to process to identify multiple latencies experienced by multiple packets processed in the SDDC.

Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Abstract: A lithography method to pattern a first semiconductor wafer is disclosed. An optical mask is positioned over the first semiconductor wafer. A first region of the first semiconductor wafer is patterned by directing light from a light source through transparent regions of the optical mask. A second region of the first semiconductor wafer is patterned by directing energy from an energy source to the second region, wherein the patterning of the second region comprises direct-beam writing.

Abstract: A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.

Abstract: A photoresist film and application thereof are provided. The photoresist film has a thickness T with a unit of ?m, and when the photoresist film is characterized by ultraviolet-visible spectroscopy, the photoresist film has an absorbance A405nm at 405 nm and an absorbance A436nm at 436 nm, wherein 0<A405nm/T?0.006 and 0<A436nm/T?0.005, and the thickness T is 60 ?m to 600 ?m.

Abstract: An ultra-wideband antenna device is disposed on a casing of an electronic device. The ultra-wideband antenna device includes radio frequency terminals, a first antenna module, a second antenna module, and a switch module. The radio frequency terminals, the first antenna module and the switch module are located in the casing. The first antenna module is located on a metal frame of the casing, and the first antenna module includes a first antenna. The second antenna module includes a second antenna, a third antenna, and a fourth antenna. The switch module is connected between the radio frequency terminals and the first antenna module. When the switch module turns on one of the radio frequency terminals and the first antenna for distance measurement, the switch module selectively turns on at least one of the second antenna, the third antenna, or the fourth antenna.