Patents by Inventor Ming Ying

Ming Ying has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12269952
    Abstract: The present invention discloses a fully bio-based, highly filled lignin-rubber masterbatch, a method for preparing same, and use thereof. The lignin-rubber masterbatch is prepared by a method comprising: (1) reacting a lignin, acetic acid, and oleic acid in the presence of a catalyst to give a modified lignin; and (2) blending the modified lignin and a rubber, and granulating to give the lignin-rubber masterbatch. The highly filled lignin-rubber masterbatch prepared by the present invention can replace the conventional reinforcing agent carbon black and provide a better reinforcing effect and higher mechanical properties for rubber materials. The present invention can also reduce the rubber content of the rubber composite materials while retaining the mechanical properties, thus featuring cost-efficiency.
    Type: Grant
    Filed: August 17, 2024
    Date of Patent: April 8, 2025
    Assignee: NANJING TECH UNIVERSITY
    Inventors: Chenjie Zhu, Haifeng Liu, Ming Li, Lei Ji, Zhiwei Chang, Yixin Feng, Zhuotao Tan, Tao Shen, Hanjie Ying
  • Patent number: 12270807
    Abstract: A reacting device of dual path synchronous immunochromatographic platform includes a seat, an upper housing, and a fluid dividing funnel. The seat contains two immunochromatographic carriers. The hollow pipe portion has two sloped structures. A force bearing portion of the fluid dividing funnel can be pressed down, so two fluid exits of the fluid dividing funnel move towards these two sloped structures. The specimen drops and is guided into these two immunochromatographic carriers respectively. A reaction result can be observable. The fluid dividing funnel can divide the specimen into two immunochromatographic carriers evenly. The sloped structure can increase the accuracy of specimen supply. Excess specimen can be scraped off for enhancing the solving accuracy. In addition, it can decrease the possibility of false positive problem.
    Type: Grant
    Filed: July 4, 2021
    Date of Patent: April 8, 2025
    Assignee: TAICHUNG VETERANS GENERAL HOSPITAL
    Inventors: Ming-Feng Wu, Hui-Chun Chang, Jing-Lian Jheng, Yi-Yun Hung, Jen-Ying Li, Hui-Chen Chen, Jiunn-Min Wang
  • Patent number: 12268784
    Abstract: A method of preparing polylactic acid (PLA) microsphere and polylactic-co-glycolic acid (PLGA) microsphere is provided, including the following steps. A first solution is provided, including polylactic acid or polylactic-co-glycolic acid and an organic solvent. A second solution is provided, including polyvinyl alcohol, sodium carboxymethyl cellulose and an aqueous solution. The first solution is added to the second solution and, at the same time, the second solution is agitated until polylactic acid is solidified to form a plurality of polylactic acid microspheres, or until polylactic-co-glycolic acid is solidified to form a plurality of polylactic-co-glycolic acid microspheres. The polylactic acid microspheres or polylactic-co-glycolic acid microspheres are collected.
    Type: Grant
    Filed: December 27, 2023
    Date of Patent: April 8, 2025
    Assignees: Taipei Medical University, Panion & BF Biotech Inc.
    Inventors: Ming-Thau Sheu, Yu-Ying Hsu, Yu-De Su, Yu-Hsuan Liu, Pu-Sheng Wei
  • Patent number: 12266852
    Abstract: An electronic device is provided. The electronic device includes a first substrate, an insulating layer, a first conductive layer and a second conductive layer. The insulating layer is overlapped with the first substrate. The second conductive layer contacts with the first conductive layer. The first conductive layer and the second conductive layer are disposed between the first substrate and the insulating layer. The second conductive layer is disposed between the first conductive layer and the insulating layer. Moreover, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the insulating layer.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: April 1, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Ping Tseng, Ker-Yih Kao, Chia-Chi Ho, Ming-Yen Weng, Hung-I Tseng, Shu-Ling Wu, Huei-Ying Chen
  • Publication number: 20250101072
    Abstract: Present invention teaches the method of using a keratin hydrolysis peptide (“KHP”) solution to enhance sweetness and flavors of tea leaves. By selectively choosing specific weights of feathers and water, and treating the mixture to a high-temperature high-pressure hydrolysis process, the resulting solution is confirmed to contain at least 253 peptides and then applied to the surface of tea leaves during sprouting stage and infused to the soil around the tea trees/plants; the increased content of L-theanine and polyphenol is separately tested and confirmed. Optionally, the KHP solution can be diluted by water, as taught in the specification, before applying to the tea leaves and the soil as taught herein.
    Type: Application
    Filed: December 8, 2023
    Publication date: March 27, 2025
    Applicant: CH Biotech R&D Co., Ltd.
    Inventors: Iou-Zen CHEN, Meng-Ying LI, Pei-Chun LIAO, Nai-Hua YE, Ming-Yuan LEE
  • Patent number: 12260917
    Abstract: A storage device for generating an identity code, includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores several first data having several bits. The second storage circuit stores several second data having several bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, and simultaneously reads the first data from the first storage circuit to form a second sequence. The reading circuit includes a processing circuit which simultaneously receives the first sequence and the second sequence, selects a first portion of the second sequence to form a target sequence according to the first sequence, and outputs the target sequence to serve as an identity code. Logical values of the bits of the first data and the second data are randomly distributed or pre-defined by a user.
    Type: Grant
    Filed: April 1, 2024
    Date of Patent: March 25, 2025
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hsuan Lin, Dai-Ying Lee, Ming-Hsiu Lee
  • Publication number: 20250098346
    Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.
    Type: Application
    Filed: January 19, 2024
    Publication date: March 20, 2025
    Inventors: Wen-Chung Chen, Chia-Yu Wei, Kuo-Cheng Lee, Cheng-Hao Chiu, Hsiu Chi Yu, Hsun-Ying Huang, Ming-Hong Su
  • Patent number: 12255136
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a via structure. The via structure is through the substrate. The via structure includes a first conductive portion, a second conductive portion, a first barrier portion, a second barrier portion, and a third barrier portion. The first conductive portion has a ring-shaped cross section. The second conductive portion is disposed at an inner side of the first conductive portion. The second conductive portion has a ring-shaped cross section. The first barrier portion is disposed at an outer side of the first conductive portion. The second barrier portion is disposed between the first conductive portion and the second conductive portion. The third barrier portion is disposed at an inner side of the second conductive portion. At least one of the first barrier portion, the second barrier portion, or the third barrier portion includes an insulating 2D material.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: March 18, 2025
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Hsien Lu, Yun-Yuan Wang, Ming-Hsiu Lee, Dai-Ying Lee
  • Patent number: 12252777
    Abstract: A physical vapor deposition (PVD) system is provided. The PVD system includes a PVD chamber defining a PVD volume within which a target material of a target is deposited onto a wafer. The PVD system includes the target in the PVD chamber. The target is configured to overlie the wafer. An edge of the target extends from a first surface of the target to a second surface of the target, opposite the first surface of the target. A first portion of the edge of the target has a first surface roughness. The first portion of the edge of the target extends at most about 6 millimeters from the first surface of the target to a second portion of the edge of the target. The second portion of the edge of the target has a second surface roughness less than the first surface roughness.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Sheng-Ying Wu, Ming-Hsien Lin, Po-Wei Wang, Hsiao-Feng Lu
  • Publication number: 20250087600
    Abstract: A semiconductor bonded structure including a first semiconductor chip, at least one second semiconductor chip, a stress adjusting structure, and a circuit layer is provided. The at least one second semiconductor chip is disposed on the first semiconductor chip and electrically connected to the first semiconductor chip. The stress adjusting structure is disposed in at least one of the first semiconductor chip and the at least one second semiconductor chip. The circuit layer is disposed on the at least one second semiconductor chip and the circuit layer is electrically connected to the at least one second semiconductor chip. A fabricating method of the semiconductor bonded structure is also provided. The semiconductor bonded structure may be applied to the fabrication of 3D NAND flash memory with high performance and high capacity.
    Type: Application
    Filed: August 19, 2024
    Publication date: March 13, 2025
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Cheng-Hsien Lu, Ming-Hsiu Lee, Dai-Ying Lee
  • Publication number: 20250079200
    Abstract: The present disclosure provides a method of determining a leakage of a semiconductor manufacturing tool. The method includes: placing a substrate including a material layer on the substrate into a chamber of the semiconductor manufacturing tool; delivering a gas into the chamber to react with the material layer; obtaining a gas composition inside the chamber; and comparing the gas composition to a referential gas composition. The leakage is determined to exist if the gas composition is substantially different from the referential gas composition.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Inventors: MING-YING PEI, YAN-HONG LIU
  • Patent number: 12243930
    Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Tai Chang, Tung-Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
  • Publication number: 20250062105
    Abstract: The present disclosure provides a mechanism for filtering an etching byproduct during semiconductor fabrication. The mechanism includes: an etching tool, configured to etch a portion of a material layer and having an outlet for discharging the etching byproduct formed from the etched portion of the material layer; a pipeline, for allowing the etching byproduct to flow through, the pipeline having a first end connected to the outlet of the etching tool and a second end distal to the first end and the etching tool; and a filter, disposed between the first end and the second end and configured to filter the etching byproduct. The filter includes a solidifier configured to solidify the etching byproduct by freezing or heating, and a medium configured to retain the etching byproduct solidified by the solidifier.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Inventors: MING-YING PEI, YAN-HONG LIU
  • Publication number: 20250062151
    Abstract: A manufacturing method of an electronic device is disclosed by the present disclosure. The manufacturing method includes providing a plurality of semiconductor elements; performing a packaging process on the plurality of semiconductor elements to form a plurality of packaged semiconductor elements, wherein the packaging process includes disposing a plurality of filling material layers respectively on a sidewall of each of the plurality of semiconductor elements; providing a substrate, wherein the substrate includes a plurality of working areas, and each of the plurality of working areas includes at least one first recess; and disposing the plurality of packaged semiconductor elements in the at least one first recess of each of the plurality of working areas through fluid transfer.
    Type: Application
    Filed: November 3, 2024
    Publication date: February 20, 2025
    Applicant: InnoLux Corporation
    Inventors: Fang-Ying Lin, Kai Cheng, Ming-Chang Lin, Tsau-Hua Hsieh, Jian-Jung Shih, Shu-Ming Kuo
  • Patent number: 12227804
    Abstract: Methods, systems, and apparatus are provided for determining whether a nucleic acid sequence imbalance exists within a biological sample. One or more cutoff values for determining an imbalance of, for example, the ratio of the two sequences (or sets of sequences) are chosen. The cutoff value may be determined based at least in part on the percentage of fetal DNA in a sample, such as maternal plasma, containing a background of maternal nucleic acid sequences. The percentage of fetal DNA can be calculated from the same or different data used to determine the cutoff value, and can use a locus where the mother is homozygous and the fetus is heterozygous. The cutoff value may be determined using many different types of methods, such as sequential probability ratio testing (SPRT).
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: February 18, 2025
    Assignee: The Chinese University of Hong Kong
    Inventors: Yuk-Ming Dennis Lo, Rossa Wai Kwun Chiu, Kwan Chee Chan, Benny Chung Ying Zee, Ka Chun Chong
  • Publication number: 20250044294
    Abstract: The present invention is related to a use of prochlorperazine (PCP), or analog thereof for treating a cancer in a subject by influencing membrane proteins and receptors and inducing alterations in the expressions of the surface marker on cancer cells and their derived extracellular vesicles. The invention method offers a novel approach for the treatment and diagnosis of cancer and metastasis. Specific surface markers serve as a potential candidate for cancer-associated extracellular vesicles (EVs) and have applications in diagnosis, prognosis, and therapeutic targeting.
    Type: Application
    Filed: July 31, 2024
    Publication date: February 6, 2025
    Applicant: National Yang Ming Chiao Tung University
    Inventors: Chi-Ying HUANG, Wei-Ni TSAI, Cayla SOLOMON, Tai-Shan CHENG, Ming-Hsi CHUANG, Ly James LEE, Peter Mu-Hsin CHANG, Yu-Tang HUANG, Thi Tuong Linh NGUYEN, Yi-Ning LO
  • Publication number: 20240413827
    Abstract: A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Yonghyun Shim, YU-Ming Ying, Guansheng Li, Delong Cui, Jun Cao
  • Patent number: 12124103
    Abstract: A liquid lens system includes a liquid lens and a heating device disposed in, on, or near the liquid lens. The liquid lens system can include a temperature sensor. The heating device can be responsive to a temperature signal generated by the temperature sensor. A camera module can include the liquid lens system. A method of operating a liquid lens includes detecting a temperature of the liquid lens and heating the liquid lens in response to the detected temperature. Various embodiments disclosed herein can reduce, impede, or prevent crosstalk between components of the liquid lens, or the effects thereof.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: October 22, 2024
    Assignees: CORNING INCORPORATED, LG INNOTEK CO. LTD.
    Inventors: Raymond Miller Karam, Daniel Ohen Ricketts, Ming Ying
  • Publication number: 20240330485
    Abstract: A private set intersection protocol in which a third party may determine intersections of a first set of a first party and a second set of a second party. The third party may not obtain any information regarding the first set or the second set other than the intersection result. The protocol may be communicatively efficient and computationally efficient to allow for secure private set intersection to be performed.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 3, 2024
    Inventors: Foo Yee YEO, Jason Hwei Ming YING
  • Patent number: D1066323
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: March 11, 2025
    Assignee: ELITEGROUP COMPUTER SYSTEMS CO., LTD.
    Inventors: Chi-Ming Chung, Wei-Ting Ying, Yi-Chun Lin, Hao-Ting Wei