Patents by Inventor Ming Yu

Ming Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154025
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal
    Type: Application
    Filed: January 10, 2024
    Publication date: May 9, 2024
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20240152476
    Abstract: Example methods and apparatus for data access are described. In one example, a memory expansion card receives a first data access request generated by a computing device based on an internal bus protocol. Then, the memory expansion card performs protocol conversion on the first data access request to obtain a second data access request in an external bus protocol format, where the external bus protocol includes a bus protocol for accessing external memory space of the computing device. Further, the memory expansion card accesses the external memory space based on the second data access request. The memory expansion card shields a difference between the bus protocols, and provides internal memory space for the computing device.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 9, 2024
    Inventors: Can CHEN, Ming CHEN, Chunyi TAN, Bowei YU
  • Publication number: 20240154749
    Abstract: This application provides a pilot signal transmission method and a related apparatus. The method includes: A first device determines a first frequency band to which a discrete RU allocated to the first device belongs; and the first device sends a first pilot signal of the first device to a second device on all pilot subcarriers included in the first frequency band. According to embodiments of this application, problems such as narrowband interference and frequency selective fading are avoided, and pilot signal transmission reliability is improved.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 9, 2024
    Inventors: Yuxin LU, Chenchen LIU, Jian YU, Yunbo LI, Ming GAN
  • Publication number: 20240151764
    Abstract: A composite intermediary device using vertical probe for wafer testing, comprising: a printed circuit board, a glass interposer and a vertical probe set; wherein the printed circuit board has printed circuit connected with a measuring apparatus, the glass interposer has multiple contact pads connected with the printed circuit, and then the probes of the vertical probe set are against the contact pads of the glass interposer and the bumps of the device under test. By a fine pitch configuration of the printed circuit and the contact pads of the glass interposer, the present invention achieves the requirements of synchronous and interleaved testing of multiple ICs.
    Type: Application
    Filed: April 17, 2023
    Publication date: May 9, 2024
    Inventors: KUN YU WU, MING TSUNG TSAI
  • Patent number: 11978675
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
  • Patent number: 11979342
    Abstract: This application relates to the field of wireless fidelity technologies, and in particular, to a resource indication method, an access point, and a station. The method includes: An access point generates a PPDU, and sends the PPDU, where the PPDU comprises a preamble puncturing information field; and where when the PPDU is in non-orthogonal frequency division multiple access (non-OFDMA) transmission mode, the preamble puncturing information field is used to indicate a puncturing status of an entire bandwidth corresponding to the PPDU; when the PPDU is in an orthogonal frequency division multiple access (OFDMA) transmission mode, the preamble puncturing information field is used to indicate a puncturing status of 80 MHz corresponding to a frequency domain fragment.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: May 7, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Mengshi Hu, Jian Yu, Ming Gan
  • Patent number: 11977745
    Abstract: A data retry-read method, a memory storage device, and a memory control circuit element are provided. The method includes: detecting a notification signal from a volatile memory module; in response to the notification signal, instructing the volatile memory module to execute N command sequences in a buffer; and after the volatile memory module executes the N command sequences, sending at least one read command sequence, according to M physical addresses involved in the N command sequences, to instruct the volatile memory module to read first data from the M physical addresses.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: May 7, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Hui Tseng, Chia-Lung Ma, Zhen-Yu Weng
  • Patent number: 11978810
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a varactor comprising a reduced surface field (RESURF) region. The method includes forming a drift region having a first doping type within a substrate. A RESURF region having a second doping type is formed within the substrate such that the RESURF region is below the drift region. A gate structure is formed on the substrate. A pair of contact regions is formed within the substrate on opposing sides of the gate structure. The contact regions respectively abut the drift region and have the first doping type, and wherein the first doping type is opposite the second doping type.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Yu Su, Chih-Wen Yao, Hsiao-Chin Tuan, Ming-Ta Lei
  • Publication number: 20240145460
    Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.
    Type: Application
    Filed: January 3, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Min WU, Ming-Dou KER, Chun-Yu LIN, Li-Wei CHU
  • Publication number: 20240145327
    Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.
    Type: Application
    Filed: December 27, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
  • Publication number: 20240138364
    Abstract: Disclosed is an air microorganism enrichment device in farms, and relates to the technical field of air microorganism collection.
    Type: Application
    Filed: January 11, 2023
    Publication date: May 2, 2024
    Inventors: Shaolun ZHAI, Chunling LI, Yan LI, Xia ZHOU, Ming LIAO, Mingfei SUN, Jianfeng ZHANG, Huahua KANG, Wenkang WEI, Ting YU
  • Publication number: 20240144568
    Abstract: Apparatuses, systems, and techniques are presented to generate digital content. In at least one embodiment, one or more neural networks are used to generate video information based at least in part upon voice information and a combination of image features and facial landmarks corresponding to one or more images of a person.
    Type: Application
    Filed: September 6, 2022
    Publication date: May 2, 2024
    Inventors: Siddharth Gururani, Arun Mallya, Ting-Chun Wang, Jose Rafael Valle da Costa, Ming-Yu Liu
  • Publication number: 20240145570
    Abstract: A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. MORE, Chandrashekhar Prakash SAVANT, Tien-Wei YU, Chia-Ming TSAI
  • Patent number: 11973076
    Abstract: The present disclosure provides a electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit and a second trigger circuit. The first trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the first reference terminal, and the second terminal is coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the second reference terminal, the second terminal is coupled to the first reference terminal via the second voltage divider, and the second trigger circuit and the first trigger circuit are in parallel connection.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fang Lai, Liang-Yu Su, Hang Fan
  • Publication number: 20240135187
    Abstract: Provided are computing systems, methods, and platforms that train query processing models, such as large language models, to perform query intent classification tasks by using retrieval augmentation and multi-stage distillation. Unlabeled training examples of queries may be obtained, and a set of the training examples may be augmented with additional feature annotations to generate augmented training examples. A first query processing model may annotate the retrieval augmented queries to generate inferred labels for the augmented training examples. A second query processing model may be trained on the inferred labels, distilling the query processing model that was trained with retrieval augmentation into a non-retrieval augmented query processing model. The second query processing model may annotate the entire set of unlabeled training examples. Another stage of distillation may train a third query processing model using the entire set of unlabeled training examples without retrieval augmentation.
    Type: Application
    Filed: October 22, 2023
    Publication date: April 25, 2024
    Inventors: Krishna Pragash Srinivasan, Michael Bendersky, Anupam Samanta, Lingrui Liao, Luca Bertelli, Ming-Wei Chang, Iftekhar Naim, Siddhartha Brahma, Siamak Shakeri, Hongkun Yu, John Nham, Karthik Raman, Raphael Dominik Hoffmann
  • Publication number: 20240134167
    Abstract: An optical path folding element includes a main body, a light absorption film layer and a matte structure. The main body has optical surface including an incident surface, a reflective surface and an emitting surface. A light enters into the optical folding element through the incident surface. The reflective surface reflects the light so as to change a traveling direction thereof. The light exits the optical folding element through the emitting surface. The light absorbing film layer is configured to reduce reflectance and provided adjacent to at least part of the optical surface, and the light absorbing film layer is in physical contact with the main body. The matte structure is disposed adjacent to at least part of the optical surface. The matte structure provides an undulating profile on a surface of the optical path folding element, and the matte structure is formed in one-piece with the main body.
    Type: Application
    Filed: September 24, 2023
    Publication date: April 25, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Ssu-Hsin LIU, Chen Wei FAN, Chien-Hsun WU, Wen-Yu TSAI, Ming-Ta CHOU
  • Patent number: 11968655
    Abstract: This application describes resource unit indication methods, access points, and stations. In an example method, a resource unit allocation subfield in a trigger frame includes a frequency band range indication and a resource unit indication. The resource unit indication is used to indicate a multi-resource unit (MRU) allocated to a station. The frequency band range indication is used to indicate a frequency band range in which a resource unit (RU) in the MRU is located. For example, the frequency band range indication is used to indicate 80 MHz in which a smallest RU in the MRU is located.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: April 23, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mengshi Hu, Jian Yu, Ming Gan
  • Patent number: 11963541
    Abstract: Provided are a device and system for generating a low frequency alternating electric field, and a signal regulating method. The device for generating a low frequency alternating electric field includes: a direct current power supply module, an input control module, a transformer, an output control module, and a discharge module. An output end of the direct current power supply module is coupled with an input end of the input control module. An output end of the input control module is coupled with a primary side winding of the transformer, one end of a secondary side winding of the transformer is coupled with an input end of the output control module, an output end of the output control module is coupled with the discharge module, and the other end of the secondary side winding of the transformer is coupled with a ground equipotential point.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 23, 2024
    Inventor: Ming Yu
  • Patent number: 11965419
    Abstract: The present invention discloses a multi-energy complementary system for a co-associated abandoned mine and a use method. The multi-energy complementary system for a co-associated abandoned mine includes a mining mechanism, a grouting mechanism and an energy mechanism. In the present invention, the mining of coal and uranium resources is realized through the mining mechanism, the subsidence and seepage reduction of the stratum is realized through the grouting mechanism, and the effective utilization of waste resources is realized through the energy mechanism. Finally, with the efficient cooperation of the three mechanisms, safe and efficient development and utilization of co-associated resources in the full life cycle are realized, and the purposes of green and efficient mining of coal and uranium resources and secondary development of a coal seam goaf are achieved, thereby facilitating the realization of dual-carbon goals and the development of low-carbon green energy.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: April 23, 2024
    Assignee: ANHUI UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Tong Zhang, Liang Yuan, Yanfang Li, Zegong Liu, Ming Tang, Xin Yang, Xiang Yu, Shuai Liu, Xin Lv
  • Patent number: D1023935
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Ya-Hao Chan, Yi-Heng Lee, Ming-Cheng Wu, Chun-Yu Chen