Abstract: A separation device includes a membrane separation module (10), an adsorption module (20), and a gas intake module (30). The membrane separation module includes a first housing (110), and a membrane assembly (130) disposed in the first housing. The first housing has a first gas inlet (121), a first gas outlet (122), and a retentate gas outlet (123). The membrane module has a permeate gas outlet, the permeate gas outlet being in communication with the first gas outlet. The adsorption module has a second housing (210) and an adsorbent layer (230) disposed in it. The second housing is disposed on the first housing and has a second gas inlet (221), a second gas outlet (222), and a desorption gas outlet (223). The second gas inlet is in communication with the first gas outlet. The gas intake module has a third gas outlet (321) in communication with the first gas inlet.

Abstract: A new variable selective etching technology for thick SOI devices. An SOI material is etched by the following steps: (1) providing an SOI wafer; (2) depositing a composite hard mask with a variable selection ratio to replace a traditional hard mask with an invariable selection ratio; (3) applying a photoresist; (4) mask making, namely defining a to-be-etched region by using a photoetching plate; (5) etching the photoresist in the defined region; (6) etching the composite hard mask; (7) removing the photoresist; (8) etching top silicon by using a second etching method at a first selection ratio; and (9) etching a buried oxide layer by using a third etching method at a second selection ratio. The new variable selective etching technology avoids the damage to a side wall of a deep trench when the buried oxide layer is etched, and does not need to use an excessive thick hard mask.

Abstract: In embodiments of the present disclosure, there is provided an approach for fact checking based on semantic graphs. According to embodiments of the present disclosure, after obtaining a text to be fact checked, a plurality of evidence sentences related to the text are retrieved from an evidence database. Then, semantic graphs of the text and the evidence sentences are constructed based on the semantic analysis, and a veracity of a statement in the text can be determined based on the semantic graphs. Embodiments of the present disclosure propose a graph-based reasoning approach for fact checking, and use the constructed semantic graphs to facilitate verification of the truthfulness of the text, thereby improving the accuracy for fact checking.

Abstract: An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.

Abstract: A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cgd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Cgd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.

Abstract: Embodiments of the invention are directed to data replication in an active-active databases having a source site and a target site. Aspects include creating a subscription activation message in a capture address space, the subscription activation message having a timestamp after a latest committed timestamp of the active-active databases and transmitting the subscription activation message to a subscription activation module of the target site of the active-active databases. Based on a determination that one or more tables associated with the subscription activation message are inactive, aspects also include repairing the one or more tables. Based on a determination that all tables associated with the subscription activation message are active, aspects include initiate replication of the capture address space from the source site to the target site with a timestamp of the latest committed timestamp.

Abstract: A termination structure of a super-junction power device has a novel polysilicon resistive field plate at the top of a termination region between a transition region and an edge of the device. By utilizing the regular distribution of potential in the field plate, an additional electric field is introduced at the top of the termination structure to limit the expansion of a non-depletion region and optimize the distribution of charges. The termination structure includes a first doping type epitaxial layer, a second doping type compensation region, a second doping type body region, a second doping type lateral connection layer, a second doping type body contact region, a first doping type source contact region, a gate oxide layer, a passivation layer, a field oxide layer, a gate electrode, a second doping type edge contact region, a polysilicon resistive field plate, a metal layer and the like.

Abstract: Aspects include monitoring, by a controller, an operational status of a tracker system that is configured to track and record a current status of a job being executed and to report completion of the job to the controller. The recording includes storing two copies of the current status, where a first copy is stored in a shared memory location accessible by the controller. In response to determining, based on the monitoring, that the tracker system is operational, waiting to receive a job completion message for the job from the tracker system and performing a job completion action based on receiving the job completion message. In response to determining that the tracker system is not operational, obtaining the current status of the job from the shared memory location and performing the job completion action based on the current status indicating that the job has completed.

Abstract: A bidirectional conduction trench gate power MOS device and a manufacturing method thereof are provided. A gate electrode, a source electrode and a drain electrode are formed on a surface of a silicon wafer to realize a bidirectional conduction and bidirectional blocking power MOS device used in an application environment such as lithium battery BMS protection.

Abstract: A method for manufacturing a semiconductor device is provided. A drift region and a compensation region are formed through a deep trench etching and a filling technology. A plurality of modulation doping regions are formed at a top of the drift region by an epitaxy and an ion implantation. A modulation region is introduced, wherein the modulation region flexibly modifies capacitance characteristics and achieve improved dynamic characteristics.

Abstract: An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.

Abstract: A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cgd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Cgd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.

Abstract: A lateral power semiconductor device includes a first type doping substrate at a bottom of the lateral power semiconductor device, a second type doping drift region, a second type heavy doping drain, a first type doping body; a first type heavy doping body contact and a second type heavy doping source, where dielectric layers are on a right side of the second type heavy doping source; the dielectric layers are arranged at intervals in a longitudinal direction in the first type doping body, and between adjacent dielectric layers in the longitudinal direction is the first type doping body; and a polysilicon is surrounded by the dielectric layer at least on a right side. Compared with conventional trench devices, the lateral power semiconductor device introduces a lateral channel, to increase a current density, thereby realizing a smaller channel on-resistance.

Abstract: The present disclosure discloses a method for displaying entity-associated information based on an electronic book and an electronic device, and the method includes: determining keywords contained in pages of the electronic book, each of the keywords indicating an entity; displaying a search entrance element corresponding to each of the keywords in the pages, the search entrance element configured to search information associated with the entity; and in response to detecting a search request triggered through the search entrance element, acquiring the information associated with the entity based on the search request and displaying the information associated with the entity.

Abstract: A power semiconductor device for improving a hot carrier injection is provided. A drain field plate is introduced at one side of a drain in a dielectric trench and connected to a drain electrode, having identical electric potential, thereby improving hole injection effects at a drain side of the dielectric trench. A shield gate field plate is introduced at one side of a source electrode in the dielectric trench and is connected to the source electrode or ground, thereby forming a shield gate. While decreasing gate drain parasitic capacitance Cgd, electron injection effects at a source electrode side of the dielectric trench are improved. With a trench etching method, the improvement of hot carrier injection can also be achieved by making carriers avoid a side wall of the dielectric trench on a path.

Abstract: A method and system for predicting a response time for a workload prior to making a hardware upgrade to a computing system. Data related to operation of the system is collected. Then a workload model of a plurality of workloads and CPU utilization for the plurality of workloads and a transaction model for each transaction within a workload of the plurality of workloads are built. Next the process determines that a characteristic of at least one workload in the plurality of workloads will change due to the hardware upgrade. As a result of the change, a new workload model for the changed workload is built based on the changed characteristic, and the response time for the workload based on the new workload model is calculated.

Abstract: A job is received. The job indicates moving one or more data to a pool storage group (PSG). The job includes resource requirements and the resource requirements include a size requirement to store the one or more data and a volume requirement to store the one or more data. A resource availability of the PSG is received. The resource availability of the PSG includes an available space on the PSG and one or more available volume on the PSG. Whether the resource availability of the PSG meets the resource requirements of the job is determined. Whether the PSG has a dynamic pool storage group (DPSG) flag indication on is determined.

Abstract: A low specific on-resistance (Ron,sp) power semiconductor device includes a power device and a transient voltage suppressor (TVS); wherein the power device comprises a gate electrode, a drain electrode, a bulk electrode, a source electrode and a parasitic body diode, the bulk electrode and the source electrode are shorted, the TVS comprises an anode electrode and a cathode electrode, the drain electrode of the power device and the anode electrode of the TVS are connected by a first metal to form a high-voltage terminal electrode, the source electrode of the power device and the cathode electrode of the TVS are connected by a second metal to form a low-voltage terminal electrode.

Abstract: An integrated power semiconductor device, includes devices integrated on a single chip. The devices include a vertical high voltage device, a first high voltage pLDMOS device, a high voltage nLDMOS device, a second high voltage pLDMOS device, a low voltage NMOS device, a low voltage PMOS device, a low voltage NPN device, and a low voltage diode device. A dielectric isolation is applied to the first high voltage pLDMOS device, the high voltage nLDMOS device, the second high voltage pLDMOS device, the low voltage NMOS device, the low voltage PMOS device, the low voltage NPN device, and the low voltage diode device. A multi-channel design is applied to the first high voltage pLDMOS device, and the high voltage nLDMOS device. A single channel design is applied to the second high voltage pLDMOS device.

Abstract: A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses.