Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO) with intra-layer variations and methods for forming such IGZO. At least a portion of a substrate is positioned in a processing chamber. A first sub-layer of an IGZO layer is formed above the at least a portion of the substrate while the at least a portion of the substrate is in the processing chamber. The first sub-layer of the IGZO layer is formed using a first set of processing conditions. A second sub-layer of the IGZO layer is formed above the first sub-layer of the IGZO layer while the at least a portion of the substrate is in the processing chamber. The second sub-layer of the IGZO layer is formed using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions.

Abstract: Disclosed herein are systems, methods, and apparatus for forming adjustable windows may include a substrate and a first conducting oxide layer formed over the substrate. The adjustable windows may further include a spectral tuning layer formed over the first conducting oxide layer and an ion conductor layer formed over the spectral tuning layer. The adjustable windows may also include an ion storage layer formed over the ion conductor layer and a second conducting oxide layer formed over the ion storage layer. In some embodiments, the spectral tuning layer may be configured to change an infrared transmissivity of the adjustable window. Furthermore, the spectral tuning layer may be configured to toggle a solar heat gain ratio coefficient of the adjustable window between two or more solar heat gain ratio coefficients.

Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A seed layer is formed above the substrate. The seed layer has a crystalline structure that is substantially dominant along the c-axis. An IGZO layer is formed above the seed layer. The seed layer may include zinc oxide. A stack of alternating seed layers and IGZO layers may be formed.

Abstract: Disclosed herein are systems, methods, and apparatus for forming windows that may include a substrate, a bottom dielectric layer formed over the substrate, and a reflective layer formed over the bottom dielectric layer. The windows may also include a conducting barrier layer formed over the reflective layer, an electrochromic layer formed over the conducting barrier layer, and an ion conductor layer formed over the electrochromic layer. The windows may further include an ion storage layer formed over the ion conductor layer and a conducting oxide layer formed over the ion storage layer. The electrochromic layer may be configured to change a transmissivity of the windows in response to a voltage being applied to the window. The windows may have an emissivity of between about 0.01 and 0.08.

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) deposition, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract: Embodiments provided herein describe abrasion resistant glass coatings and methods for forming abrasion resistant glass coatings. A glass body is provided. An abrasion resistant layer is formed above the glass body. The abrasion resistant layer includes an amorphous carbon. A pull-up layer is formed above the abrasion resistant layer. A protective layer is formed above the pull-up layer. The protective layer may include a titanium-based nitride. The pull-up lay may include tungsten oxide, zirconium oxide, manganese oxide, molybdenum oxide, titanium oxide, or a combination thereof.

Abstract: Embodiments provided herein describe transparent conductive films and methods for forming transparent conductive films. A transparent substrate is provided. A first layer is formed above the transparent substrate. The first layer includes nickel. A second layer is formed above the first layer. The second layer includes silver and palladium. A third layer is formed above the second layer. The third layer comprises nickel.

Abstract: A bi-layer seed layer can exhibit good seed property for an infrared reflective layer, together with improved thermal stability. The bi-layer seed layer can include a thin zinc oxide layer having a desired crystallographic orientation for a silver infrared reflective layer disposed on a bottom layer having a desired thermal stability. The thermal stable layer can include aluminum, magnesium, or bismuth doped tin oxide (AlSnO, MgSnO, or BiSnO), which can have better thermal stability than zinc oxide but poorer lattice matching for serving as a seed layer template for silver (111).

Abstract: Embodiments provided herein describe a low-e panel and a method for forming a low-e panel. A transparent substrate is provided. A metal oxide layer is formed over the transparent substrate. The metal oxide layer includes a first element, a second element, and a third element. A reflective layer is formed over the transparent substrate. The first element may include tin or zinc. The second element and the third element may each include tin, zinc, antimony, silicon, strontium, titanium, niobium, zirconium, magnesium, aluminum, yttrium, lanthanum, hafnium, or bismuth. The metal oxide layer may also include nitrogen.

Abstract: Methods are provided to use data obtained from a single wavelength ellipsometer to determine the refractive index of materials as a function of wavelength for thin conductive films. The methods may be used to calculate the refractive index spectrum as a function of wavelength for thin films of metals, and conductive materials such as conductive metal nitrides or conductive metal oxides.

Abstract: Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a first substrate. The first substrate may have a first side and a second side. The low emissivity panels may also include a magnetic fluid layer deposited over the first side of the first substrate and a reflective layer deposited over the second side of the first substrate. The magnetic fluid layer may include magnetic particles. The reflective layer may include a conductive material configured to conduct an electrical current and generate a magnetic field. The magnetic field may be configured to change an orientation of the magnetic particles in the magnetic fluid layer and a transmissivity of the magnetic fluid layer within a visible spectrum. The low emissivity panels may also include a first bus and a second bus deposited along opposite edges of the reflective layer and electrically connected to the reflective layer.

Abstract: Embodiments provided herein describe a low-e panel and a method for forming a low-e panel. A transparent substrate is provided. A metal oxynitride layer is formed over the transparent substrate. The metal oxynitride layer includes a first metal and a second metal. A reflective layer is formed over the transparent substrate.

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract: Provided is High Productivity Combinatorial (HPC) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors. The tested barrier layers may include all or at least two of nickel, chromium, titanium, and aluminum. In some embodiments, the barrier layers include oxygen. This combination allows using relative thin barrier layers (e.g., 5-30 Angstroms thick) that have high transparency yet provide sufficient protection to the silver reflector. The amount of nickel in a barrier layer may be 5-10% by weight, chromium—25-30%, titanium and aluminum—30%-35% each. The barrier layer may be co-sputtered in a reactive or inert-environment using one or more targets that include all four metals. An article may include multiple silver reflectors, each having its own barrier layer.

Abstract: Diffusion of silver from LED reflector layers is blocked by 10-50 nm barrier layers of nickel-titanium (NiTi) alloys. Optionally, the alloys also include one or more of tungsten (W), niobium (Nb), aluminum (Al), vanadium (V), tantalum (Ta), or chromium (Cr). These barriers may omit the noble-metal (e.g., platinum or gold) cap used with silver barriers based on other materials.

Abstract: The electrical and optical performance of silver LED reflective contacts in III-V devices such as GaN LEDs is limited by silver's tendency to agglomerate during annealing processes and to corrode on contact with silver-reactive materials elsewhere in the device (for example, gallium or aluminum). Agglomeration and reaction are prevented, and crystalline morphology of the silver layer may be optimized, by forming a diffusion-resistant transparent conductive layer between the silver and the source of silver-reacting metal, (2) doping the silver or the diffusion-resistant transparent conductive layer for improved adhesion to adjacent layers, or (3) doping the silver with titanium, which in some embodiments prevents agglomeration and promotes crystallization of the silver in the preferred <111> orientation.

Abstract: Methods to improve the reflection of light emitting devices are disclosed. A method consistent with the present disclosure includes forming a light generating layer over a site-isolated region of a substrate. Next, forming a first transparent conductive layer over the light generating layer. Forming a low refractive index material over the first transparent conductive layer, and in time, forming a second transparent conductive layer over the low refractive index material. Subsequently, forming a reflective material layer thereon. Accordingly, methods consistent with the present disclosure may form a plurality of light emitting devices in various site-isolated regions on a substrate.

Abstract: A magnetron assembly including one or more magnetrons each forming a closed plasma loop on the sputtering face of the target. The target may include multiple strip targets on which respective strip magnetrons roll and are partially supported on a common support plate through a spring mechanism. The strip magnetron may be a two-level folded magnetron in which each magnetron forms a folded plasma loop extending between lateral sides of the strip target and its ends meet in the middle of the target. The magnets forming the magnetron may be arranged in a pattern having generally uniform straight portions joined by curved portion in which extra magnet positions are available near the corners to steer the plasma track. Multiple magnetrons, possibly flexible, may be resiliently supported on a scanned support plate and individually partially supported by rollers on the back of one or more targets.

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from doped metal oxides and/or nitrides. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature annealing. In some embodiments, the breakdown voltage of a current limiting layer may be at least about 8V. Some examples of such current limiting layers include titanium oxide doped with niobium, tin oxide doped with antimony, and zinc oxide doped with aluminum. Dopants and base materials may be deposited as separate sub-layers and then redistributed by annealing or may be co-deposited using reactive sputtering or co-sputtering. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layer while maintaining their performance.