Patents by Inventor Minoru Harada

Minoru Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190266713
    Abstract: A versatile template generation unit cuts a first region in which a similarity level to a template image is a first similarity level and a second region in which the similarity level to the template image is a second similarity level different from the first similarity level, from an input image including an alignment mark, to generate a versatile template image.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 29, 2019
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Naoaki KONDO, Minoru HARADA, Yuji TAKAGI, Takehiro HIRAI
  • Publication number: 20190217438
    Abstract: A substrate processing apparatus which causes a processing tape to abut against a processing object, including: a tape supply reel configured to supply the processing tape; a tape recovery reel configured to recover the processing tape; a recovery motor configured to apply a torque to the tape recovery reel; a tape feed motor configured to feed the processing tape between the tape supply reel and the tape recovery reel; and a control unit configured to control the tape feed motor, wherein the control unit controls the torque of the recovery motor depending on a change in an outer diameter of a roll of the processing tape wound by the tape recovery reel such that tension applied to the processing tape is constant, using a feed length of the tape fed by the tape feed motor and a thickness of the processing tape.
    Type: Application
    Filed: January 11, 2019
    Publication date: July 18, 2019
    Inventors: Minoru Harada, Takahiro Nanjo, Hiroyuki Takenaka, Naoki Matsuda
  • Publication number: 20190139210
    Abstract: Provided is a defect classification apparatus classifying images of defects of a sample included in images obtained by capturing the sample, the apparatus including an image storage unit for storing the images of the sample acquired by an external image acquisition unit, a defect class storage unit for storing types of defects included in the images of the sample, an image processing unit for extracting images of defects from the images from the sample, processing the extracted images of defects and generating a plurality of defect images, a classifier learning unit for learning a defect classifier using the images of defects of the sample extracted by the image processing unit and data of the plurality of generated defect images, and a defect classification unit for processing the images of the sample by using the classifier learned by the classifier learning unit, to classify the images of defects of the sample.
    Type: Application
    Filed: May 24, 2016
    Publication date: May 9, 2019
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Naoaki KONDO, Takehiro HIRAI, Minoru HARADA, Yuji TAKAGI
  • Patent number: 10229812
    Abstract: An inspection method uses a charged particle microscope to observe a sample and view a defect site or a circuit pattern. A plurality of images is detected by a plurality of detectors and a mixed image is generated by automatically adjusting and mixing weighting factors required when the plurality of images are synthesized with each other. The sample is irradiated and scanned with a charged particle beam so that the plurality of detectors arranged at different positions from the sample detects a secondary electron or a reflected electron generated from the sample. The mixed image is generated by mixing the plurality of images of the sample with each other for each of the plurality of detectors, which are obtained by causing each of the plurality of detectors arranged at the different positions to detect the secondary electron or the reflected electron. The generated mixed image is displayed on a screen.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 12, 2019
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Minoru Harada, Yuji Takagi, Takehiro Hirai
  • Patent number: 10203851
    Abstract: Provided is a GUI including: an unadded pane region that hierarchically displays folders which are sets of images having no class information added thereto; an image pane region that displays the images displayed in the unadded pane region, the displayed images having no classification added thereto; and a class pane region that displays images having classification added thereto, wherein by externally inputting class information for one image having the class information added thereto, the input class information is displayed.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 12, 2019
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Yohei Minekawa, Yuji Takagi, Minoru Harada, Takehiro Hirai, Ryo Nakagaki
  • Publication number: 20180240225
    Abstract: A sample observation device images a sample placed on a movable table by irradiating and scanning the sample with a charged particle beam of a microscope. A degraded image having poor image quality and a high quality image having satisfactory image quality which are acquired at the same location of the sample by causing the charged particle microscope to change an imaging condition for imaging the sample are stored. An estimation process parameter is calculated for estimating the high quality image from the degraded image by using the stored degraded image and high quality image. A high quality image estimation unit processes the degraded image obtained by causing the charged particle microscope to image the desired site of the sample by using the calculated estimation process parameter. Thereby, the high quality image obtained at the desired site is estimated, and then the estimated high quality image is output.
    Type: Application
    Filed: February 16, 2018
    Publication date: August 23, 2018
    Inventors: Minoru HARADA, Yuji TAKAGI, Naoaki KONDO, Takehiro HIRAI
  • Publication number: 20180174000
    Abstract: In a defect classification operation in which ADC and visual classification are both used, a problem with the visual classification in the related art is solved, and then the high-reliability performance evaluation of the ADC and the update of the ADC learning data set are made possible, using both the ADC and the visual classification, or both the ADC and one other classification apparatus.
    Type: Application
    Filed: June 4, 2015
    Publication date: June 21, 2018
    Inventors: Yuji TAKAGI, Minoru HARADA, Takehiro HIRAI
  • Patent number: 9922414
    Abstract: In order to reduce the amount of time it takes to collect images of defects, this defect inspection device is provided with the following: a read-out unit that reads out positions of defects in a semiconductor wafer that have already been detected; a first imaging unit that takes, at a first magnification, a reference image of a chip other than the chip where one of the read-out defects is; a second imaging unit that takes, at the first magnification, a first defect image that contains the read-out defect; a defect-position identification unit that identifies the position of the defect in the first defect image taken by the second imaging unit by comparing said first defect image with the reference image taken by the first imaging unit; a third imaging unit that, on the basis of the identified defect position, takes a second defect image at a second magnification that is higher than the first magnification; a rearrangement unit that rearranges the read-out defects in an order corresponding to a path that goes
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: March 20, 2018
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Yuji Takagi, Minoru Harada, Masashi Sakamoto, Takehiro Hirai
  • Publication number: 20180025482
    Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.
    Type: Application
    Filed: September 29, 2017
    Publication date: January 25, 2018
    Inventors: Minoru HARADA, Ryo NAKAGAKI, Fumihiko FUKUNAGA, Yuji TAKAGI
  • Publication number: 20180019097
    Abstract: An inspection method uses a charged particle microscope to observe a sample and view a defect site or a circuit pattern. A plurality of images is detected by a plurality of detectors and a mixed image is generated by automatically adjusting and mixing weighting factors required when the plurality of images are synthesized with each other. The sample is irradiated and scanned with a charged particle beam so that the plurality of detectors arranged at different positions from the sample detects a secondary electron or a reflected electron generated from the sample. The mixed image is generated by mixing the plurality of images of the sample with each other for each of the plurality of detectors, which are obtained by causing each of the plurality of detectors arranged at the different positions to detect the secondary electron or the reflected electron. The generated mixed image is displayed on a screen.
    Type: Application
    Filed: December 21, 2015
    Publication date: January 18, 2018
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Minoru HARADA, Yuji TAKAGI, Takehiro HIRAI
  • Patent number: 9811897
    Abstract: The purpose of the present invention is to easily extract, from samples to be observed, defect candidates that can be labeled as a defect or “nuisance” (a part for which a manufacturing tolerance or the like is erroneously detected) and to allow parameters pertaining to observation processing to be easily adjusted. This defect observation method comprises: an imaging step to image, on the basis of defect information from an inspection device, an object to be inspected and obtain a defect image and a reference image corresponding to the defect image; a parameter determining step to determine a first parameter to be used in the defect extraction by using a first feature set distribution acquired from the reference image and the defect image captured in the imaging step and a second feature net distribution acquired from the reference image; and an observing step to observe using the first parameter determined in the parameter determining step.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: November 7, 2017
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Minoru Harada, Yuji Takagi, Ryo Nakagaki, Takehiro Hirai, Hirohiko Kitsuki
  • Patent number: 9799112
    Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: October 24, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Minoru Harada, Ryo Nakagaki, Fumihiko Fukunaga, Yuji Takagi
  • Publication number: 20170282132
    Abstract: An ozone water production device (1) includes: flow rate controllers (4, 5) that each control a flow rate of gas which is a raw material; a flow rate meter (12) that measures a flow rate of water which is a raw material; a booster pump (13) that controls pressure of the water; an ozone water generating unit (8) that generates ozone water by mixing ozone gas and the water; and a pressure sensor (17) that measures pressure of the ozone water which is to be supplied to a use point (19). The booster pump (13) controls the pressure of the water such that the pressure of the ozone water measured by the pressure sensor (17) is constant. The flow rate controllers (4, 5) each control the flow rate of the gas in accordance with the flow rate of the water measured by the flow rate meter (12).
    Type: Application
    Filed: September 9, 2015
    Publication date: October 5, 2017
    Inventors: Suguru OZAWA, Minoru HARADA, Munehito TAKAHASHI
  • Patent number: 9569836
    Abstract: Cases in which defects are analyzed in a manufacturing process stage in which a pattern is not formed or in a manufacturing process in which a pattern formed on a lower layer does not appear in the captured image are increasing. However, in these cases, there is a problem of not being able to synthesize a favorable reference image and failing to detect a defect when a periodic pattern cannot be recognized in the pattern. In the present invention, a defect occupation rate, which is the percentage of an image being inspected occupied by a defect region, is found, it is determined whether the defect occupation rate is higher or lower than a threshold, and, in accordance with the determination results, it is determined whether to create, as the reference image, an image comprising pixels having the average luminance value of the luminance values of a plurality of pixels contained in the image being inspected.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: February 14, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takehiro Hirai, Ryo Nakagaki, Minoru Harada
  • Patent number: 9401015
    Abstract: In automatic defect classification, a classification recipe must be set for each defect observation device. If a plurality of devices operate at the same stage, the classification class in the classification recipes must be the same. Problems have arisen whereby differences occur in the classification class in different devices when a new classification recipe is created. This defect classification system has a classification recipe storage unit; an information specification unit, the stage of a stored image, and device information. A corresponding defect specification unit specifies images of the same type of defect from images obtained from different image pickup devices at the same stage. An image conversion unit converts the images obtained from the different image pickup devices at the same stage into comparable similar images; and a recipe update unit records the classification classes in the classification recipes corresponding to the specified images of the same type of defect.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: July 26, 2016
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yohei Minekawa, Yuji Takagi, Minoru Harada, Takehiro Hirai, Ryo Nakagaki
  • Patent number: 9390490
    Abstract: In performing a programmed-point inspection of a circuit pattern using a review SEM, stable inspection can be performed while suppressing the generation of a false report even when a variation in a circuit pattern to be inspected is large. SEM images that are obtained by sequentially imaging a predetermined circuit pattern using the review SEM are stored into a storage unit. Images that meet a set condition are selected from the stored SEM images, and averaged to create an average image (GP image). By performing pattern check by GP comparison using this GP image, an inspection can be performed while suppressing the generation of a false report even when a variation in the circuit patterns is large.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: July 12, 2016
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Yuji Takagi, Minoru Harada, Ryo Nakagaki, Naoki Hosoya, Toshifumi Honda, Takehiro Hirai
  • Patent number: 9342879
    Abstract: A method for reviewing defect, comprising the steps of: as an image acquisition step, imaging a surface of a sample using arbitrary image acquisition condition selected from a plurality of image acquisition conditions and obtaining a defect image; as a defect position calculation step, proceeding the defect image obtained by the image acquisition step and calculating a defect position on the surface of the sample; as a defect detection accuracy calculation step, obtaining a defect detection accuracy of the defect position calculated by the defect position calculation step; and as a conclusion determination step, determinating whether the defect detection accuracy obtained by the defect detection accuracy calculation step meets a predetermined requirement or not; wherein until it is determined that the defect detection accuracy obtained by the defect detection accuracy calculation step meets a predetermined in the conclusion determination step, the image acquisition condition is selected from the plurality of
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: May 17, 2016
    Assignee: Hitachi Hich-Technologies Corporation
    Inventors: Yohei Minekawa, Kenji Nakahira, Minoru Harada, Takehiro Hirai, Ryo Nakagaki
  • Patent number: 9311697
    Abstract: Disclosed is a method of inspecting an object to be inspected in a semiconductor manufacturing process, for resolving the problem to increase defect detection sensitivity. An image capture means is used to image capture a designated area of the object to be inspected; a defect is detected in the captured image; a circuit pattern is recognized from the captured image; a characteristic value is computed, relating to an image tone and shape, from the detected defect; a characteristic value is computed, relating to the image tone and shape, from the recognized circuit pattern; either a specified defect or circuit pattern is filtered and extracted from the detected defect and the recognized circuit pattern; a mapping characteristic value is determined from the characteristic value of either the filtered and extracted specified defect or circuit pattern; and the distribution of the determined characteristic values is displayed onscreen in a map format.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: April 12, 2016
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Minoru Harada, Ryo Nakagaki, Takehiro Hirai, Naoki Hosoya
  • Publication number: 20160019682
    Abstract: In order to reduce the amount of time it takes to collect images of defects, this defect inspection device is provided with the following: a read-out unit that reads out positions of defects in a semiconductor wafer that have already been detected; a first imaging unit that takes, at a first magnification, a reference image of a chip other than the chip where one of the read-out defects is; a second imaging unit that takes, at the first magnification, a first defect image that contains the read-out defect; a defect-position identification unit that identifies the position of the defect in the first defect image taken by the second imaging unit by comparing said first defect image with the reference image taken by the first imaging unit; a third imaging unit that, on the basis of the identified defect position, takes a second defect image at a second magnification that is higher than the first magnification; a rearrangement unit that rearranges the read-out defects in an order corresponding to a path that goes
    Type: Application
    Filed: January 27, 2014
    Publication date: January 21, 2016
    Inventors: Yuji TAKAGI, Minoru HARADA, Masashi SAKAMOTO, Takehiro HIRAI
  • Patent number: RE47779
    Abstract: An electronic musical instrument is equipped with plural series combinations of switches and resistors and a piezoelectric transducer associated with a movable member for producing electric signals representative of player's intentions to music sound to be generated, and a signal processing system processes the signals for generating the music sound; the signal processing system has a voltage discriminator so that the plural series combinations are connected in parallel to the voltage discriminator through a single conductive line; a vibration absorber is inserted between the movable member and the piezoelectric transducer so that the piezoelectric transducer exactly converts the motion of the movable member to the electric signal at each player's manipulation.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: December 24, 2019
    Assignee: YAMAHA CORPORATION
    Inventors: So Tanaka, Minoru Harada