Patents by Inventor Minoru Kubo
Minoru Kubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106672Abstract: A content generation apparatus capable of easily confirming content data, the information of which is registered in a blockchain, is provided. An image pickup apparatus generates an image file and then immediately calculates a hash value of the image file, and transmits image file information including the hash value to a management system. In response to receipt of a registration completion notification indicating that a process of registering the image file information in a blockchain is completed, the image pickup apparatus stores registration-completed information indicating that the image file information is registered in the blockchain, relating to the image file.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: DAIYU UENO, KEIICHIRO KUBO, NAOHIKO TSUCHIDA, MINORU SAKAIDA, ATSUSHI FUJITA, KEISUKE TANAKA
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Publication number: 20240070250Abstract: A content generation apparatus capable of guaranteeing that a provider of a content is a generator of the content is provided. The content generation apparatus that generates a content according to an instruction received from a user includes an acquisition unit configured to acquire biometric information of the user, a biometric authentication unit configured to perform biometric authentication of the user based on the biometric information of the user, a hash value generation unit configured to generate a hash value of the content in a case that the biometric authentication of the user has succeeded, and a communication unit configured to transmit the content and information of the content to a management server that registers the hash value and the information of the content in a blockchain. The information of the content includes result information indicating a result of the biometric authentication of the user.Type: ApplicationFiled: August 30, 2023Publication date: February 29, 2024Inventors: NAOHIKO TSUCHIDA, DAIYU UENO, MINORU SAKAIDA, ATSUSHI FUJITA, KEIICHIRO KUBO, KEISUKE TANAKA
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Patent number: 7248544Abstract: Disclosed is an optical head in which position adjustment of a photodetector light receiving surface or component parts may be simplified, production costs may be reduced and operational reliability may be improved. The optical head includes a light source 22, radiating light of a preset wavelength, an objective lens 27 for condensing the outgoing light from the light source 22 on an optical disc 2 and for condensing the return light from the optical disc 2, a beam splitter 25 for branching the optical path of the return light reflected by the optical disc 2, and for collimating the branched return light so as to be parallel to the outgoing light from the light source 22, a composite optical component including a splitting prism 30 arranged on a site of incidence of the branched return light for spatially splitting the return light, and a light receiving unit for receiving plural return light beams spatially split by the splitting prism 30 for producing focusing error signals.Type: GrantFiled: May 20, 2004Date of Patent: July 24, 2007Assignee: Sony CorporationInventors: Masahiro Saito, Norio Fukasawa, Kiyoshi Toyota, Junichi Suzuki, Minoru Kubo, Souichi Murakami
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Patent number: 7244972Abstract: In a field effect transistor, an Si layer 11, an SiC (Si1?yCy) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.Type: GrantFiled: June 17, 2004Date of Patent: July 17, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Minoru Kubo, Yo Ichikawa, Akira Asai, Takahiro Kawashima
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Patent number: 7170110Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.Type: GrantFiled: November 9, 2004Date of Patent: January 30, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
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Patent number: 7135721Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.Type: GrantFiled: June 22, 2004Date of Patent: November 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Toyoda, Koichiro Yuki, Takeshi Takagi, Teruhito Ohnishi, Minoru Kubo
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Patent number: 7105449Abstract: A thermal cleaning of a substrate that has been subjected to wet cleaning is carried out under a high vacuum atmosphere to remove an oxide film remaining on the substrate. Thereafter, a thermal cleaning is carried out under a hydrogen atmosphere to remove contamination such as carbon or the like. At this time, the oxide film has already been removed and therefore contamination is effectively removed by a relatively low temperature and short duration thermal cleaning. Thus, problems such as the degradation of the profile of the impurity concentration in the impurity diffusion layer which has been formed over the substrate are prevented.Type: GrantFiled: October 27, 2000Date of Patent: September 12, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsuya Nozawa, Minoru Kubo, Tohru Saitoh
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Patent number: 7049198Abstract: An S1-yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterojunction is formed between the Si and Si1-yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the S1-yGey layer can be suppressed. As a result, the Si/Si1-yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.Type: GrantFiled: March 4, 2003Date of Patent: May 23, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichiro Yuki, Tohru Saitoh, Minoru Kubo, Kiyoshi Ohnaka, Akira Asai, Koji Katayama
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Patent number: 6965107Abstract: An Al film is formed on a cap wafer and the Al film is patterned into a ring-shaped film. Dry etching is performed by using the ring-shaped film as a mask to form a drum portion enclosing a recess portion to provide a vacuum dome. After forming a depth of cut into the substrate portion of the cap wafer, the cap wafer is placed on a main body wafer having an infrared area sensor formed thereon. Then, the ring-shaped film of the cap wafer and the ring-shaped film of the main body wafer are joined to each other by pressure bonding to form a ring-shaped joining portion.Type: GrantFiled: March 4, 2004Date of Patent: November 15, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyoshi Komobuchi, Minoru Kubo, Masahiko Hashimoto, Michio Okajima, Shinichi Yamamoto
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Patent number: 6930026Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and SiC microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.Type: GrantFiled: April 16, 2003Date of Patent: August 16, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiko Kanzawa, Katsuya Nozawa, Tohru Saitoh, Minoru Kubo
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Patent number: 6919253Abstract: A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.Type: GrantFiled: February 7, 2003Date of Patent: July 19, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tohru Saitoh, Katsuya Nozawa, Minoru Kubo, Shigetaka Aoki
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Patent number: 6890834Abstract: An Al film is formed on a cap wafer and the Al film is patterned into a ring-shaped film. Dry etching is performed by using the ring-shaped film as a mask to form a drum portion enclosing a recess portion to provide a vacuum dome. After forming a depth of cut into the substrate portion of the cap wafer, the cap wafer is placed on a main body wafer having an infrared area sensor formed thereon. Then, the ring-shaped film of the cap wafer and the ring-shaped film of the main body wafer are joined to each other by pressure bonding to form a ring-shaped joining portion.Type: GrantFiled: June 6, 2002Date of Patent: May 10, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyoshi Komobuchi, Minoru Kubo, Masahiko Hashimoto, Michio Okajima, Shinichi Yamamoto
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Publication number: 20050093020Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.Type: ApplicationFiled: November 9, 2004Publication date: May 5, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
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Publication number: 20050066887Abstract: A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.Type: ApplicationFiled: February 7, 2003Publication date: March 31, 2005Inventors: Tohru Saitoh, Katsuya Nozawa, Minoru Kubo, Shigetaka Aoki
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Patent number: 6872989Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.Type: GrantFiled: February 24, 2003Date of Patent: March 29, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
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Patent number: 6852602Abstract: A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0?x1<1 and 0<y1<1) having a small Ge mole fraction, e.g., a Si0.785Ge0.2C0.015 layer 13, and a Si1-x2-y2Gex2Cy2 layer (0<x2?1 and 0?y2<1) (where x1<x2 and y1>y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.Type: GrantFiled: January 30, 2002Date of Patent: February 8, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiko Kanzawa, Tohru Saitoh, Katsuya Nozawa, Minoru Kubo, Yoshihiro Hara, Takeshi Takagi, Takahiro Kawashima
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Publication number: 20050025002Abstract: Disclosed is an optical head in which position adjustment of a photodetector light receiving surface or component parts may be simplified, production costs may be reduced and operational reliability may be improved. The optical head includes a light source 22, radiating light of a preset wavelength, an objective lens 27 for condensing the outgoing light from the light source 22 on an optical disc 2 and for condensing the return light from the optical disc 2, a beam splitter 25 for branching the optical path of the return light reflected by the optical disc 2, and for collimating the branched return light so as to be parallel to the outgoing light from the light source 22, a composite optical component including a splitting prism 30 arranged on a site of incidence of the branched return light for spatially splitting the return light, and a light receiving unit for receiving plural return light beams spatially split by the splitting prism 30 for producing focusing error signals.Type: ApplicationFiled: May 20, 2004Publication date: February 3, 2005Inventors: Masahiro Saito, Norio Fukasawa, Kiyoshi Toyota, Junichi Suzuki, Minoru Kubo, Souichi Murakami
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Patent number: 6844227Abstract: In a field effect transistor, an Si layer, an SiC (Si1-yCy) channel layer, a CN gate insulating film made of a carbon nitride layer (CN) and a gate electrode are deposited in this order on an Si substrate. The thickness of the SiC channel layer is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region and a drain region are formed on opposite sides of the SiC channel layer, and a source electrode and a drain electrode are provided on the source region and the drain region, respectively.Type: GrantFiled: December 26, 2001Date of Patent: January 18, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Minoru Kubo, Yo Ichikawa, Akira Asai, Takahiro Kawashima
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Publication number: 20040232441Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.Type: ApplicationFiled: June 22, 2004Publication date: November 25, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kenji Toyoda, Koichiro Yuki, Takeshi Takagi, Teruhito Ohnishi, Minoru Kubo
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Publication number: 20040227169Abstract: In a field effect transistor, an Si layer 11, an SiC (Si1-yCy) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.Type: ApplicationFiled: June 17, 2004Publication date: November 18, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Minoru Kubo, Yo Ichikawa, Akira Asai, Takahiro Kawashima