Patents by Inventor Minoru Kubo

Minoru Kubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10435399
    Abstract: The present invention provides a heterocyclic compound having a HDAC inhibitory action, and useful for the treatment of central nervous system diseases including neurodegenerative disease, and the like, and a medicament comprising the compound. The present invention relates to a compound represented by the formula (I): wherein each symbol is as defined in the specification, or a salt thereof.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 8, 2019
    Assignee: Takeda Pharmaceutical Company Limited
    Inventors: Masahiro Ito, Hideyuki Sugiyama, Osamu Kubo, Fumiaki Kikuchi, Takeshi Yasui, Keiko Kakegawa, Zenichi Ikeda, Tohru Miyazaki, Yasuyoshi Arikawa, Tomohiro Okawa, Jinichi Yonemori, Akinori Toita, Takuto Kojima, Yasutomi Asano, Ayumu Sato, Hironobu Maezaki, Shinobu Sasaki, Hironori Kokubo, Misaki Homma, Minoru Sasaki, Yasuhiro Imaeda
  • Publication number: 20190221696
    Abstract: This photovoltaic power generation device is provided with: a mounting bracket which is fixed to a roof and on which a frame, arranged on the ridge-side end of a solar cell module, and a frame, arranged on the eave-side end of a solar cell module, are mounted; and a fixing bracket which is arranged in the space between the frame and the frame, and which is fixed to the mounting bracket and holds said frames from above.
    Type: Application
    Filed: March 22, 2019
    Publication date: July 18, 2019
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Koichi Kubo, Tomohide Yoshida, Mamoru Arimoto, Naofumi Hayashi, Minoru Higuchi
  • Publication number: 20190222170
    Abstract: This photovoltaic power generation device is provided with: a mounting bracket which is fixed to a roof and on which a frame, arranged on the ridge-side end of a solar cell module, and a frame, arranged on the eave-side end of a solar cell module, are mounted; and a securing bracket for securing the frames to the mounting bracket. The ridge-side edge of the mounting bracket is inclined in the eaves-ridge direction and the girder direction of the roof.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Applicant: Panasonic Intellectual Property Management Co., Lt d.
    Inventors: Koichi Kubo, Naofumi Hayashi, Minoru Higuchi
  • Publication number: 20190145368
    Abstract: A first controller includes a start control section and a passage determination section. After activating a second starter to start cranking, the start control section stops the operation of the second starter and starts the motor operation of the first starter at a predetermined timing. The passage determination section determines whether a predetermined passage conditional expression holds after cranking is started by the second starter. The start control section stops the operation of the second starter and starts the motor operation of the first starter if the passage conditional expression holds before the engine passes the first compression top dead center, regardless of whether the engine has passed the first compression top dead center.
    Type: Application
    Filed: June 15, 2017
    Publication date: May 16, 2019
    Applicant: DENSO CORPORATION
    Inventors: Takuro NAKAOKA, Akihiro IMURA, Mitsuru SHIBANUMA, Yuki KUBO, Minoru OKAMIYA, Suguru MIZUNO
  • Publication number: 20190135799
    Abstract: The present invention provides a heterocyclic compound having a HDAC inhibitory action, and useful for the treatment of central nervous system diseases including neurodegenerative disease, and the like, and a medicament comprising the compound. The present invention relates to a compound represented by the formula (I): wherein each symbol is as defined in the specification, or a salt thereof.
    Type: Application
    Filed: July 30, 2018
    Publication date: May 9, 2019
    Inventors: Masahiro ITO, Hideyuki SUGIYAMA, Osamu KUBO, Fumiaki KIKUCHI, Takeshi YASUI, Keiko KAKEGAWA, Zenichi IKEDA, Tohru MIYAZAKI, Yasuyoshi ARIKAWA, Tomohiro OKAWA, Jinichi YONEMORI, Akinori TOITA, Takuto KOJIMA, Yasutomi ASANO, Ayumu SATO, Hironobu MAEZAKI, Shinobu SASAKI, Hironori KOKUBO, Misaki HOMMA, Minoru SASAKI, Yasuhiro IMAEDA
  • Patent number: 7248544
    Abstract: Disclosed is an optical head in which position adjustment of a photodetector light receiving surface or component parts may be simplified, production costs may be reduced and operational reliability may be improved. The optical head includes a light source 22, radiating light of a preset wavelength, an objective lens 27 for condensing the outgoing light from the light source 22 on an optical disc 2 and for condensing the return light from the optical disc 2, a beam splitter 25 for branching the optical path of the return light reflected by the optical disc 2, and for collimating the branched return light so as to be parallel to the outgoing light from the light source 22, a composite optical component including a splitting prism 30 arranged on a site of incidence of the branched return light for spatially splitting the return light, and a light receiving unit for receiving plural return light beams spatially split by the splitting prism 30 for producing focusing error signals.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: July 24, 2007
    Assignee: Sony Corporation
    Inventors: Masahiro Saito, Norio Fukasawa, Kiyoshi Toyota, Junichi Suzuki, Minoru Kubo, Souichi Murakami
  • Patent number: 7244972
    Abstract: In a field effect transistor, an Si layer 11, an SiC (Si1?yCy) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: July 17, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Kubo, Yo Ichikawa, Akira Asai, Takahiro Kawashima
  • Patent number: 7170110
    Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: January 30, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
  • Patent number: 7135721
    Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: November 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Toyoda, Koichiro Yuki, Takeshi Takagi, Teruhito Ohnishi, Minoru Kubo
  • Patent number: 7105449
    Abstract: A thermal cleaning of a substrate that has been subjected to wet cleaning is carried out under a high vacuum atmosphere to remove an oxide film remaining on the substrate. Thereafter, a thermal cleaning is carried out under a hydrogen atmosphere to remove contamination such as carbon or the like. At this time, the oxide film has already been removed and therefore contamination is effectively removed by a relatively low temperature and short duration thermal cleaning. Thus, problems such as the degradation of the profile of the impurity concentration in the impurity diffusion layer which has been formed over the substrate are prevented.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: September 12, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsuya Nozawa, Minoru Kubo, Tohru Saitoh
  • Patent number: 7049198
    Abstract: An S1-yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterojunction is formed between the Si and Si1-yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the S1-yGey layer can be suppressed. As a result, the Si/Si1-yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: May 23, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichiro Yuki, Tohru Saitoh, Minoru Kubo, Kiyoshi Ohnaka, Akira Asai, Koji Katayama
  • Patent number: 6965107
    Abstract: An Al film is formed on a cap wafer and the Al film is patterned into a ring-shaped film. Dry etching is performed by using the ring-shaped film as a mask to form a drum portion enclosing a recess portion to provide a vacuum dome. After forming a depth of cut into the substrate portion of the cap wafer, the cap wafer is placed on a main body wafer having an infrared area sensor formed thereon. Then, the ring-shaped film of the cap wafer and the ring-shaped film of the main body wafer are joined to each other by pressure bonding to form a ring-shaped joining portion.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: November 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyoshi Komobuchi, Minoru Kubo, Masahiko Hashimoto, Michio Okajima, Shinichi Yamamoto
  • Patent number: 6930026
    Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and SiC microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: August 16, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiko Kanzawa, Katsuya Nozawa, Tohru Saitoh, Minoru Kubo
  • Patent number: 6919253
    Abstract: A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: July 19, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tohru Saitoh, Katsuya Nozawa, Minoru Kubo, Shigetaka Aoki
  • Patent number: 6890834
    Abstract: An Al film is formed on a cap wafer and the Al film is patterned into a ring-shaped film. Dry etching is performed by using the ring-shaped film as a mask to form a drum portion enclosing a recess portion to provide a vacuum dome. After forming a depth of cut into the substrate portion of the cap wafer, the cap wafer is placed on a main body wafer having an infrared area sensor formed thereon. Then, the ring-shaped film of the cap wafer and the ring-shaped film of the main body wafer are joined to each other by pressure bonding to form a ring-shaped joining portion.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: May 10, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyoshi Komobuchi, Minoru Kubo, Masahiko Hashimoto, Michio Okajima, Shinichi Yamamoto
  • Publication number: 20050093020
    Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.
    Type: Application
    Filed: November 9, 2004
    Publication date: May 5, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
  • Publication number: 20050066887
    Abstract: A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.
    Type: Application
    Filed: February 7, 2003
    Publication date: March 31, 2005
    Inventors: Tohru Saitoh, Katsuya Nozawa, Minoru Kubo, Shigetaka Aoki
  • Patent number: 6872989
    Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: March 29, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
  • Patent number: 6852602
    Abstract: A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0?x1<1 and 0<y1<1) having a small Ge mole fraction, e.g., a Si0.785Ge0.2C0.015 layer 13, and a Si1-x2-y2Gex2Cy2 layer (0<x2?1 and 0?y2<1) (where x1<x2 and y1>y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: February 8, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiko Kanzawa, Tohru Saitoh, Katsuya Nozawa, Minoru Kubo, Yoshihiro Hara, Takeshi Takagi, Takahiro Kawashima
  • Publication number: 20050025002
    Abstract: Disclosed is an optical head in which position adjustment of a photodetector light receiving surface or component parts may be simplified, production costs may be reduced and operational reliability may be improved. The optical head includes a light source 22, radiating light of a preset wavelength, an objective lens 27 for condensing the outgoing light from the light source 22 on an optical disc 2 and for condensing the return light from the optical disc 2, a beam splitter 25 for branching the optical path of the return light reflected by the optical disc 2, and for collimating the branched return light so as to be parallel to the outgoing light from the light source 22, a composite optical component including a splitting prism 30 arranged on a site of incidence of the branched return light for spatially splitting the return light, and a light receiving unit for receiving plural return light beams spatially split by the splitting prism 30 for producing focusing error signals.
    Type: Application
    Filed: May 20, 2004
    Publication date: February 3, 2005
    Inventors: Masahiro Saito, Norio Fukasawa, Kiyoshi Toyota, Junichi Suzuki, Minoru Kubo, Souichi Murakami