Patents by Inventor Minoru Kubo
Minoru Kubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6815735Abstract: A semiconductor layer 30 of a graded SiGe-HDTMOS is constructed of an upper Si film 12, an Si buffer layer 13, an Si1−xGex film 14 and an Si cap layer 15. The region between a source region 20a and drain region 20b of the semiconductor layer 30 includes a high concentration n-type Si body region 22 and an n Si region 23, an Si cap region 25 and an SiGe channel region 24. A Ge composition ratio x of the Si1−xGex film 14 is made to increase from the Si buffer layer 13 to the Si cap layer 15. For the p-type HDTMOS, the electron current component of the substrate current decreases.Type: GrantFiled: December 13, 2002Date of Patent: November 9, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
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Publication number: 20040173751Abstract: An Al film is formed on a cap wafer and the Al film is patterned into a ring-shaped film. Dry etching is performed by using the ring-shaped film as a mask to form a drum portion enclosing a recess portion to provide a vacuum dome. After forming a depth of cut into the substrate portion of the cap wafer, the cap wafer is placed on a main body wafer having an infrared area sensor formed thereon. Then, the ring-shaped film of the cap wafer and the ring-shaped film of the main body wafer are joined to each other by pressure bonding to form a ring-shaped joining portion.Type: ApplicationFiled: March 4, 2004Publication date: September 9, 2004Inventors: Hiroyoshi Komobuchi, Minoru Kubo, Masahiko Hashimoto, Michio Okajima, Shinichi Yamamoto
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Publication number: 20040142579Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.Type: ApplicationFiled: December 17, 2002Publication date: July 22, 2004Inventors: Kiyoyuki Morita, Shoji Miyake, Michihito Ueda, Takashi Ohtsuka, Takashi Nichikawa, Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
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Patent number: 6759697Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.Type: GrantFiled: June 16, 2003Date of Patent: July 6, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Toyoda, Koichiro Yuki, Takeshi Takagi, Teruhito Ohnishi, Minoru Kubo
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Patent number: 6756278Abstract: A lateral heterojunction bipolar transistor comprises a first semiconductor layer in a mesa configuration disposed on an insulating layer, a second semiconductor layer formed by epitaxial growth on the side surfaces of the first semiconductor layer and having a band gap different from that of the first semiconductor layer, and a third semiconductor layer formed by epitaxial growth on the side surfaces of the second semiconductor layer and having a band gap different from that of the second semiconductor layer. The first semiconductor layer serves as a collector of a first conductivity type. At least a part of the second semiconductor layer serves as an internal base layer of a second conductivity type. At least a part of the third semiconductor layer serves as an emitter operating region of the first conductivity type. The diffusion of an impurity is suppressed in the internal base formed by epitaxial growth.Type: GrantFiled: October 11, 2002Date of Patent: June 29, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichiro Yuki, Minoru Kubo
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Publication number: 20040092085Abstract: A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0≦x1<1 and O<yl<1) having a small Ge mole fraction, e.g., a Si0.785Ge0.2C0.015 layer 13, and a Si1x-2-y2Gex2Cy2 layer (0<x2≦1 and 0≦y2<1) (where x1<x2 and y1>y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.Type: ApplicationFiled: December 12, 2002Publication date: May 13, 2004Inventors: Yoshihiko Kanzawa, Tohru Saitoh, Katsuya Nozawa, Minoru Kubo, Yoshihiro Hara, Takeshi Takagi, Takahiro Kawashima
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Patent number: 6720587Abstract: An initial estimated value of a process condition is set, and a structure of an element of a semiconductor device is estimated by a process simulator, after which an estimated value of a physical amount measurement value is calculated. Then, an actual measurement value of a physical amount of the element of the semiconductor device, which is obtained by an optical evaluation method, and a theoretical calculated value thereof are compared with each other, so as to obtain a probable structure of the measured semiconductor device element by using, for example, a simulated annealing, or the like. A process condition in a process for other semiconductor device elements can be corrected by using the results.Type: GrantFiled: February 4, 2002Date of Patent: April 13, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsuya Nozawa, Tohru Saitoh, Minoru Kubo, Yoshihiko Kanzawa
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Patent number: 6674100Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.Type: GrantFiled: April 5, 2002Date of Patent: January 6, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Minoru Kubo, Katsuya Nozawa, Masakatsu Suzuki, Takeshi Uenoyama, Yasuhito Kumabuchi
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Patent number: 6660393Abstract: A B-doped Si1−x−yGexCy layer 102 (where 0<x<1, 0.01≦y<1) is epitaxially grown on a Si substrate 101 using a UHV-CVD process. In the meantime, in-situ doping is performed using B2H6 as a source gas of boron (B) which is an impurity (dopant). Next, the Si1−x−yGexCy layer 102 is annealed to form a B-doped Si1−x−yGexCy crystalline layer 103. In this case, the annealing temperature is set preferably at between 700° C. and 1200° C., both inclusive, and more preferably at between 900° C. and 1000° C., both inclusive.Type: GrantFiled: March 10, 2003Date of Patent: December 9, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tohru Saitoh, Yoshihiko Kanzawa, Katsuya Nozawa, Minoru Kubo
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Publication number: 20030213977Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.Type: ApplicationFiled: June 16, 2003Publication date: November 20, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kenji Toyoda, Koichiro Yuki, Takeshi Takagi, Teruhito Ohnishi, Minoru Kubo
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Patent number: 6649496Abstract: After the surface of a Si substrate (1) has been pretreated, an SiGeC layer (2) is formed on the Si substrate (1) using an ultrahigh vacuum chemical vapor deposition (UHV-CVD) apparatus. During this process step, the growth temperature of the SiGeC layer (2) is set at 490° C. or less and Si2H6, GeH4 and SiH3CH3 are used as Si, Ge and C sources, respectively, whereby the SiGeC layer (2) with good crystallinity can be formed.Type: GrantFiled: November 21, 2001Date of Patent: November 18, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiko Kanzawa, Katsuya Nozawa, Tohru Saitoh, Minoru Kubo
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Patent number: 6645836Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and Sic microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.Type: GrantFiled: November 21, 2001Date of Patent: November 11, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiko Kanzawa, Katsuya Nozawa, Tohru Saitoh, Minoru Kubo
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Publication number: 20030201497Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.Type: ApplicationFiled: February 24, 2003Publication date: October 30, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
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Publication number: 20030203599Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and SiC microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.Type: ApplicationFiled: April 16, 2003Publication date: October 30, 2003Applicant: Matsushita Electric Industrial Co. , Ltd.Inventors: Yoshihiko Kanzawa, Katsuya Nozawa, Tohru Saitoh, Minoru Kubo
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Publication number: 20030183921Abstract: An Al film is formed on a cap wafer and the Al film is patterned into a ring-shaped film. Dry etching is performed by using the ring-shaped film as a mask to form a drum portion enclosing a recess portion to provide a vacuum dome. After forming a depth of cut into the substrate portion of the cap wafer, the cap wafer is placed on a main body wafer having an infrared area sensor formed thereon. Then, the ring-shaped film of the cap wafer and the ring-shaped film of the main body wafer are joined to each other by pressure bonding to form a ring-shaped joining portion.Type: ApplicationFiled: June 6, 2002Publication date: October 2, 2003Inventors: Hiroyoshi Komobuchi, Minoru Kubo, Masahiko Hashimoto, Michio Okajima, Shinichi Yamamoto
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Patent number: 6620665Abstract: A process control is performed for fabricating both a wafer for a device including a Ge-containing semiconductor film and a wafer for a device, for example, including no Ge-containing semiconductor film on a common fabrication line. When the wafer including the Ge-containing semiconductor film is to be subjected to high-temperature treatment at 700° C. or more in the state of the Ge-containing semiconductor film being substantially exposed, the Ge-containing semiconductor film is covered with a cap layer made of Si or the like before the high-temperature treatment. The cap layer may be formed on the common fabrication line. However, if the formation of the cap layer itself involves high temperature of 700° C. or more, it is performed on a fabrication line separate from the common fabrication line. Alternatively, the cap layer may be formed on a fabrication line separate from the common fabrication line and the high-temperature treatment at 700° C.Type: GrantFiled: March 14, 2001Date of Patent: September 16, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Gaku Sugahara, Tohru Saitoh, Minoru Kubo, Teruhito Ohnishi
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Publication number: 20030165697Abstract: A B-doped Si1-x-yGexCy layer 102 (where 0<x<1, 0.01≦y<1) is epitaxially grown on a Si substrate 101 using a UHV-CVD process. In the meantime, in-situ doping is performed using B2H6 as a source gas of boron (B) which is an impurity (dopant). Next, the Si1-x-yGexCy layer 102 is annealed to form a B-doped Si1-x-yGexCy crystalline layer 103. In this case, the annealing temperature is set preferably at between 700° C. and 1200° C., both inclusive, and more preferably at between 900° C. and 1000° C., both inclusive.Type: ApplicationFiled: March 10, 2003Publication date: September 4, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Tohru Saitoh, Yoshihiko Kanzawa, Katsuya Nozawa, Minoru Kubo
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Publication number: 20030162335Abstract: An S1-yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterojunction is formed between the Si and Si1-yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the S1-yGey layer can be suppressed. As a result, the Si/Si1-yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.Type: ApplicationFiled: March 4, 2003Publication date: August 28, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Koichiro Yuki, Tohru Saitoh, Minoru Kubo, Kiyoshi Ohnaka, Akira Asai, Koji Katayama
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Publication number: 20030146473Abstract: A semiconductor layer 30 of a graded SiGe-HDTMOS is constructed of an upper Si film 12, an Si buffer layer 13, an Si1−xGex film 14 and an Si cap layer 15. The region between a source region 20a and drain region 20b of the semiconductor layer 30 includes a high concentration n-type Si body region 22 and an n Si region 23, an Si cap region 25 and an SiGe channel region 24. A Ge composition ratio x of the Si1−xGex film 14 is made to increase from the Si buffer layer 13 to the Si cap layer 15. For the p-type HDTMOS, the electron current component of the substrate current decreases.Type: ApplicationFiled: December 13, 2002Publication date: August 7, 2003Inventors: Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
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Patent number: 6597016Abstract: An Si1−yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterounction junction is formed between the Si and Si1−yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the Si1−yGey layer can be suppressed. As a result, the Si/Si1−yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.Type: GrantFiled: January 13, 2000Date of Patent: July 22, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichiro Yuki, Tohru Saitoh, Minoru Kubo, Kiyoshi Ohnaka, Akira Asai, Koji Katayama