Abstract: A method for patterning a stack having a patterned organic mask with a plurality of mask features including sidewalls and tops, a hardmask and an etch layer, wherein the patterned organic mask is positioned over the hardmask which is positioned over the etch layer is provided. An atomic layer deposition is deposited, wherein the depositing the atomic layer deposition controllably trims the plurality of mask features of the patterned organic mask. The atomic layer deposition is broken through. The hardmask is selectively etched with respect to the patterned organic mask, wherein the atomic layer deposition reduces faceting of the plurality of mask features of the patterned organic mask during the selective etching.

Abstract: Methods and apparatuses for spacer profile control using atomic layer deposition (ALD) in multi-patterning processes are described herein. A silicon oxide spacer is deposited over a patterned core material and a target layer of a substrate in a multi-patterning scheme. A first thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a first oxidation condition that includes an oxidation time, a plasma power, and a substrate temperature. A second thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a second oxidation condition, where the second oxidation condition is different than the first oxidation condition by one or more parameters. After etching the patterned core material, a resulting profile of the silicon oxide spacer is dependent at least in part on the first and second oxidation conditions.

Abstract: Methods and apparatuses for spacer profile control using atomic layer deposition (ALD) in multi-patterning processes are described herein. A silicon oxide spacer is deposited over a patterned core material and a target layer of a substrate in a multi-patterning scheme. A first thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a first oxidation condition that includes an oxidation time, a plasma power, and a substrate temperature. A second thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a second oxidation condition, where the second oxidation condition is different than the first oxidation condition by one or more parameters. After etching the patterned core material, a resulting profile of the silicon oxide spacer is dependent at least in part on the first and second oxidation conditions.

Abstract: A method for etching features in a stack comprising a patterned hardmask over a carbon based mask layer is provided. A pattern is transferred from the patterned hardmask to the carbon based mask layer, comprising providing a flow of a transfer gas comprising an oxygen containing component and at least one of SO2 or COS, forming the transfer gas into a plasma, providing a bias of greater than 10 volts, and stopping the flow of the transfer gas. A post treatment is provided, comprising providing a flow of a post treatment gas comprising at least one of He, Ar, N2, H2, or NH3, wherein the flow is provided to maintain a processing pressure of between 50 mTorr and 500 mTorr inclusive, forming the post treatment gas into a plasma, providing a bias of greater than 20 volts, and stopping the flow of the post treatment gas.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: A method for controlling an etch operation which is a rapid alternating process having etch and passivation phases is described. The method includes (a) supplying source power to an inductive coil of a plasma chamber, (b) initiating supply of a first process gas that flows along a distance separating a mass flow controller and the chamber, (c) detecting an optical signal from plasma generated within the chamber, with the optical signal being analyzed to identify a predefined change in amplitude relative to time, (d) triggering activation of bias power upon identifying the predefined change, the bias power being held active for a predefined amplitude duration during which the etch phase is primarily active, (e) initiating supply of a second process gas during a period in which the passivation phase is primarily active and the bias power is inactive, and (f) repeating (b)-(e) for additional cycles while processing an etch operation.

Abstract: A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: A method provides an EAMR transducer. The EAMR transducer is coupled with a laser and has an ABS configured to reside in proximity to a media during use. The method includes providing an NFT using an NFT mask. The NFT resides proximate to the ABS and focuses the laser energy onto the media. A portion of the NFT mask is removed, forming a heat sink mask covering part of the NFT. Optical material(s) are deposited, covering the heat sink mask and the NFT. The heat sink mask is removed, providing an aperture in the optical material(s). A heat sink corresponding to the aperture is provided. The heat sink bottom is thermally coupled with the NFT. A write pole for writing to the media and coil(s) for energizing the write pole are provided. The write pole has a bottom surface thermally coupled with the top surface of the heat sink.

Abstract: A method provides an EAMR transducer. The EAMR transducer is coupled with a laser and has an ABS configured to reside in proximity to a media during use. The EAMR transducer includes an NFT for focusing the energy onto the media. A sacrificial layer is deposited on the NFT and a mask having an aperture provided on the sacrificial layer. A portion of the sacrificial layer exposed by the aperture is removed to form a trench above the NFT. A heat sink is then provided. At least part of the heat sink resides in the trench. The heat sink is thermally coupled to the NFT. Optical material(s) are provided around the heat sink. A write pole configured to write to a region of the media is also provided. The write pole is thermally coupled with the top of the heat sink. Coil(s) for energizing the write pole are also provided.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber.

Abstract: A rapid alternating process system and method of operating a rapid alternating process system includes a rapid alternating process chamber, a plurality of process gas sources coupled to the rapid alternating process chamber, wherein each one of the plurality of process gas sources includes a corresponding process gas source flow controller, a bias signal source coupled to the rapid alternating process chamber, a process gas detector coupled to the rapid alternating process chamber, a rapid alternating process chamber controller coupled to the rapid alternating process chamber, the bias signal source, the process gas detector and the plurality of process gas sources, the rapid alternating process chamber controller including logic for initiating a first rapid alternating process phase including: logic for inputting a first process gas into a rapid alternating process chamber, logic for detecting the first process gas in the rapid alternating process chamber, and logic for applying a corresponding first phase b

Abstract: Nanoimprint lithography templates are provided. One such template includes a template base and a plurality of pattern layers of a first material. Each pattern layer is separated from an adjacent pattern layer by a spacing layer of a second material that is different from the first material. Such a template also includes a plurality of pillars of a third material that is different from the first material. Each of the pillars separates two adjacent pattern layers, and each of the pattern layers has a respective portion which protrudes from the spacing layers and from the pillars.

Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.

Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.

Abstract: Methods for forming nanodots and/or a patterned material are provided. One such method involves forming a first patterning material over a base. Blades of a nanoimprint lithography template are placed within the first patterning material, wherein the blades extend along the base in a first direction. With the blades within the first patterning material, the first patterning material are cured. The blades are removed from the first patterning material to form a patterned first patterning material. The base is etched using the patterned first patterning material as a pattern to form openings in the base. The patterned first patterning material is removed from the base. A second patterning material is formed over the base and within the openings in the base. Blades of a nanoimprint lithography template are placed within the second patterning material, wherein the blades extend along the base in a second direction, which is generally perpendicular with respect to the first direction.