Patents by Inventor Mirzafer Abatchev
Mirzafer Abatchev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110294294Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.Type: ApplicationFiled: August 11, 2011Publication date: December 1, 2011Applicant: Micron Technology, Inc.Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar M. Subramanian
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Patent number: 8011090Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.Type: GrantFiled: May 19, 2008Date of Patent: September 6, 2011Assignee: Micron Technology, Inc.Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar M. Subramanian
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Patent number: 7857982Abstract: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the feature pattern therein as a mask. After the partial etching, at least one of the hard mask layers is etched selectively relative to the substrate material and remaining of the hard mask layers. After etching at least one of the hard mask layers, the feature is further etched into the substrate material using at least an innermost of the hard mask layers as a mask. After the further etching, the innermost hard mask layer and any hard mask layers remaining thereover are removed from the substrate, and at least a portion of the feature is incorporated into an integrated circuit.Type: GrantFiled: July 19, 2005Date of Patent: December 28, 2010Assignee: Micron Technology, Inc.Inventors: Mirzafer Abatchev, Gurtej S. Sandhu, Aaron R. Wilson, Tony Schrock
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Publication number: 20100144132Abstract: Methods for forming nanodots and/or a patterned material are provided. One such method involves forming a first patterning material over a base. Blades of a nanoimprint lithography template are placed within the first patterning material, wherein the blades extend along the base in a first direction. With the blades within the first patterning material, the first patterning material are cured. The blades are removed from the first patterning material to form a patterned first patterning material. The base is etched using the patterned first patterning material as a pattern to form openings in the base. The patterned first patterning material is removed from the base. A second patterning material is formed over the base and within the openings in the base. Blades of a nanoimprint lithography template are placed within the second patterning material, wherein the blades extend along the base in a second direction, which is generally perpendicular with respect to the first direction.Type: ApplicationFiled: February 15, 2010Publication date: June 10, 2010Inventors: Krupakar M. Subramanian, Mirzafer Abatchev
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Patent number: 7662299Abstract: A method for forming a template useful for nanoimprint lithography comprises forming at least one pillar which provides a topographic feature extending from a template base. At least one conformal pattern layer and one conformal spacing layer, and generally a plurality of alternating pattern layers and spacing layers, are formed over the template base and pillar. A planarized filler layer is formed over the pattern and spacing layers, then the filler, the spacing layer and the pattern layer are partially removed, for example using mechanical polishing, to expose the pillar. One or more etches are performed to remove at least a portion of the pillar, the filler, and the spacing layer to result in the pattern layer protruding from the spacing layer and providing the template pattern.Type: GrantFiled: August 30, 2005Date of Patent: February 16, 2010Assignee: Micron Technology, Inc.Inventors: Krupakar M. Subramanian, Mirzafer Abatchev
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Publication number: 20090225602Abstract: Floating-gate memory cells having a split floating gate facilitate decreased sensitivity to localized defects in the tunnel dielectric and/or the intergate dielectric. Such memory cells also permit storage of more than one bit per cell. Methods of the various embodiments facilitate fabrication of floating gate segments having dimensions less than the capabilities of the lithographic processed used to form the gate stacks.Type: ApplicationFiled: May 13, 2009Publication date: September 10, 2009Inventors: Gurtej S. Sandhu, Mirzafer Abatchev
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Patent number: 7547599Abstract: Floating-gate memory cells having a split floating gate facilitate decreased sensitivity to localized defects in the tunnel dielectric layer and/or the intergate dielectric layer. Such memory cells also permit storage of more than one bit per cell. Methods of the various embodiments facilitate fabrication of floating gate segments having dimensions less than the capabilities of the lithographic processed used to form the gate stacks.Type: GrantFiled: May 26, 2005Date of Patent: June 16, 2009Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Mirzafer Abatchev
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Method of depositing a layer comprising silicon, carbon, and fluorine onto a semiconductor substrate
Patent number: 7473645Abstract: The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz—comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz—comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.Type: GrantFiled: November 16, 2006Date of Patent: January 6, 2009Assignee: Micron Technology, Inc.Inventors: Mirzafer Abatchev, Krupakar M. Subramanian -
Publication number: 20080290527Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.Type: ApplicationFiled: August 5, 2008Publication date: November 27, 2008Applicant: MICRON TECHNOLOGY, INC.Inventors: Mirzafer Abatchev, Gurtej Sandhu
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Publication number: 20080261349Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.Type: ApplicationFiled: May 19, 2008Publication date: October 23, 2008Applicant: MICRON TECHNOLOGY, INC.Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar M. Subramanian
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Patent number: 7429536Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form sumperimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.Type: GrantFiled: May 23, 2005Date of Patent: September 30, 2008Assignee: MICRON Technology, Inc.Inventors: Mirzafer Abatchev, Gurtej Sandhu
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Patent number: 7393789Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.Type: GrantFiled: September 1, 2005Date of Patent: July 1, 2008Assignee: MICRON Technology, Inc.Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar M. Subramanian
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Patent number: 7291563Abstract: The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz-comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz-comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.Type: GrantFiled: August 18, 2005Date of Patent: November 6, 2007Assignee: Micron Technology, Inc.Inventors: Mirzafer Abatchev, Krupakar M. Subramanian
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Publication number: 20070212889Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.Type: ApplicationFiled: March 9, 2006Publication date: September 13, 2007Inventors: Mirzafer Abatchev, Krupakar Subramanian, Baosuo Zhou
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Publication number: 20070161251Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.Type: ApplicationFiled: March 1, 2007Publication date: July 12, 2007Applicant: Micron Technology, Inc.Inventors: Luan Tran, William Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer Abatchev, Gurtej Sandhu, D. Durcan
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Publication number: 20070148984Abstract: Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern.Type: ApplicationFiled: March 8, 2007Publication date: June 28, 2007Applicant: Micron Technology, Inc.Inventors: Mirzafer Abatchev, Gurtej Sandhu, Luan Tran, William Rericha, D. Durcan
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Publication number: 20070138526Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.Type: ApplicationFiled: January 31, 2007Publication date: June 21, 2007Applicant: Micron Technology, Inc.Inventors: Luan Tran, William Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer Abatchev, Gurtej Sandhu, D. Durcan
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Publication number: 20070128856Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.Type: ApplicationFiled: February 1, 2007Publication date: June 7, 2007Applicant: Micron Technology, Inc.Inventors: Luan Tran, William Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi (Jenny) Bai, Zhiping Yin, Paul Morgan, Mirzafer Abatchev, Gurtej Sandhu, D. Durcan
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Publication number: 20070123050Abstract: A carbon or carbon-containing underlayer, which is used as a mask, is patterned using a process comprising, in one specific embodiment, boron trichloride and oxygen under specified processing conditions to etch the underlayer. The underlayer is then used as a mask to etch a layer below the underlayer, such as a semiconductor wafer or a layer formed as part of a semiconductor wafer substrate assembly. Various processing conditions are described, as is the formation of various features using embodiments of the inventive process.Type: ApplicationFiled: November 14, 2005Publication date: May 31, 2007Inventors: Baosuo Zhou, Mirzafer Abatchev, Krupakar Subramanian
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Method of depositing a layer comprising silicon, carbon, and flourine onto a semiconductor substrate
Publication number: 20070066068Abstract: The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz—comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz—comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.Type: ApplicationFiled: November 16, 2006Publication date: March 22, 2007Inventors: Mirzafer Abatchev, Krupakar Subramanian